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    Nonvolatile semiconductor memory device having element isolating region of trench type
    43.
    发明授权
    Nonvolatile semiconductor memory device having element isolating region of trench type 有权
    具有沟槽型元件隔离区域的非易失性半导体存储器件

    公开(公告)号：US07939406B2

    公开(公告)日：2011-05-10

    申请号：US12435842

    申请日：2009-05-05

    申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

    摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

    摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

    Semiconductor memory integrated circuit and its manufacturing method
    44.
    发明授权
    Semiconductor memory integrated circuit and its manufacturing method 失效
    半导体存储器集成电路及其制造方法

    公开(公告)号：US07785954B2

    公开(公告)日：2010-08-31

    申请号：US12630499

    申请日：2009-12-03

    申请人： Seiichi Mori

    发明人： Seiichi Mori

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

    摘要： A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film (22), second-layer polycrystalline silicon film (24) and third-layer polycrystalline silicon film 28, and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.

    摘要翻译： 制造半导体存储器集成电路的方法，旨在提高其外围电路的性能和可靠性包括在电池阵列区域中形成隧道氧化膜（21a）的步骤，用于高压电路的栅极氧化膜（21b）和 栅极氧化膜（21c），用于在外围电路中分别实现最佳厚度值的低电压电路，并用第一层多晶硅膜（22）覆盖它们。 之后，用器件隔离绝缘膜（14）形成并埋设器件隔离槽（13）。 第一层多晶硅膜（24）是非掺杂膜，在器件分离之后，第二层多晶硅膜（24）在电池阵列区域中掺杂有磷，形成由第一层多晶硅膜 多层多晶硅膜（22）和第二层多晶硅膜（24）。 在外围电路中，栅电极由包括第一层多晶硅，膜（22），第二层多晶硅膜（24）和第三层多晶硅膜28的多层膜制成，杂质为离子 然后分别在相应的最佳条件下分别施加到相应的晶体管区域。

    Nonvolatile semiconductor memory device having element isolating region of trench type
    45.
    发明授权
    Nonvolatile semiconductor memory device having element isolating region of trench type 有权
    具有沟槽型元件隔离区域的非易失性半导体存储器件

    公开(公告)号：US07573092B2

    公开(公告)日：2009-08-11

    申请号：US11556026

    申请日：2006-11-02

    申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

    摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

    摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

    Semiconductor device and method of manufacturing the same
    46.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07557401B2

    公开(公告)日：2009-07-07

    申请号：US11405538

    申请日：2006-04-18

    申请人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

    发明人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76897 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521

    摘要： A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.

    摘要翻译： 半导体器件包括与有源区相邻的元件隔离绝缘膜，形成在有源区中的半导体衬底上的栅极绝缘膜，位于栅极绝缘膜上的成对栅电极，位于栅极之间的有源区上的接触插塞 电极，位于栅极电极上的一对第一上部线，位于栅电极上的第二上部线，以及栅电极的上表面和栅电极的侧表面之上的阻挡膜。 元件隔离绝缘膜相对于半导体衬底的上表面具有上表面的第一高度，并且相对于半导体衬底的另一上表面具有另一上表面的第二高度。 第一个高度小于第二个高度。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE
    48.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
    具有元件分离区域的非挥发性半导体存储器件

    公开(公告)号：US20070057310A1

    公开(公告)日：2007-03-15

    申请号：US11556026

    申请日：2006-11-02

    申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

    摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

    摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。