Systems and methods for non-binary decoding
    43.
    发明授权
    Systems and methods for non-binary decoding 有权
    用于非二进制解码的系统和方法

    公开(公告)号:US08560929B2

    公开(公告)日:2013-10-15

    申请号:US13167764

    申请日:2011-06-24

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 公开了一种数据处理电路,其包括:数据检测器电路,第一符号约束布置电路和第二符号约束布置电路。 数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合,以产生包括多个非二进制符号的检测输出。 第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。 来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。 第二符号约束布置电路可操作以接收第二输入数据集并且根据第二布置算法重排第二数据输入以产生解码数据集。 用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

    Systems and Methods for Non-Binary Decoding
    45.
    发明申请
    Systems and Methods for Non-Binary Decoding 有权
    非二进制解码的系统和方法

    公开(公告)号:US20120331370A1

    公开(公告)日:2012-12-27

    申请号:US13167764

    申请日:2011-06-24

    IPC分类号: G06F11/08

    摘要: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 公开了一种数据处理电路,其包括:数据检测器电路,第一符号约束布置电路和第二符号约束布置电路。 数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合,以产生包括多个非二进制符号的检测输出。 第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。 来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。 第二符号约束排列电路可操作以接收第二输入数据集并且根据第二布置算法重新布置第二数据输入以产生解码的数据集。 用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

    Amplitude-based approach for detection and classification of hard-disc defect regions
    46.
    发明授权
    Amplitude-based approach for detection and classification of hard-disc defect regions 失效
    基于幅度的硬盘缺陷区域检测和分类方法

    公开(公告)号:US08045283B2

    公开(公告)日:2011-10-25

    申请号:US12729312

    申请日:2010-03-23

    IPC分类号: G11B27/36 G11B5/02

    摘要: In a hard-disc drive, a defect region on the hard disc is classified as corresponding to either thermal asperity (TA) or media defect (MD) by generating two statistical measures. A first measure (e.g., α1) is based on (i) the magnitudes of one or both of signal values (e.g., equalizer input or output signal values) and the corresponding expected values of those signal values and (ii) the signs of one or both of the signal values and the expected signal values. A second measure (e.g., α2) is based on the magnitudes of one or both of the signal values and the expected signal values, but not the signs of either the signal values or the expected signal values. The two measures are then compared to determine whether the defect region corresponds to TA or MD.

    摘要翻译: 在硬盘驱动器中,通过产生两个统计测量值将硬盘上的缺陷区域分类为对应于热粗糙度(TA)或介质缺陷(MD)。 第一测量(例如,α1)基于(i)信号值(例如,均衡器输入或输出信号值)中的一个或两个的大小以及那些信号值的相应期望值,以及(ii)一个 或信号值和预期信号值两者。 第二量度(例如,α2)基于信号值和预期信号值中的一个或两个的幅度,而不是信号值或期望信号值的符号。 然后比较两个测量值以确定缺陷区域是否对应于TA或MD。

    Mixed domain FFT-based non-binary LDPC decoder
    47.
    发明授权
    Mixed domain FFT-based non-binary LDPC decoder 有权
    基于混合域FFT的非二进制LDPC解码器

    公开(公告)号:US08819515B2

    公开(公告)日:2014-08-26

    申请号:US13340951

    申请日:2011-12-30

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.

    摘要翻译: 本发明的各种实施例涉及用于解码数据的方法和装置,更具体地涉及用于在混合域FFT的非二进制LDPC解码器中解码数据的方法和装置。 例如,在一个实施例中,一种装置包括消息处理电路,其可操作以处理可变节点消息并检查对数域中的节点消息,以及可操作以执行基于快速傅里叶变换的低密度奇偶校验解码器中的校验节点计算电路 在真实域中检查节点计算。 消息处理电路和校验节点计算电路进行迭代层解码。

    CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING
    49.
    发明申请
    CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING 有权
    使用列表解码纠正错误的代码中的错误

    公开(公告)号:US20140075264A1

    公开(公告)日:2014-03-13

    申请号:US13611158

    申请日:2012-09-12

    IPC分类号: H03M13/05 H03M13/13

    摘要: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

    摘要翻译: 通信系统的接收路径包括纠错解码器,错误检测解码器和码字调节器。 误差校正解码器对接收的码字进行纠错解码,以生成有效的码字。 错误检测解码器对有效码字执行错误检测解码,以确定有效码字是否是发送的正确码字。 如果有效码字不是正确的码字,则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。 错误检测解码器对经调整的有效码字执行错误检测解码,以确定调整后的有效码字是否为正确码字。 当纠错解码器产生不正确的有效码字时,调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。