公开(公告)号：US20220077318A1

公开(公告)日：2022-03-10

申请号：US17524766

申请日：2021-11-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20210390920A1

公开(公告)日：2021-12-16

申请号：US17401396

申请日：2021-08-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/32

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20210249445A1

公开(公告)日：2021-08-12

申请号：US17156769

申请日：2021-01-25

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

公开(公告)号：US20200312885A1

公开(公告)日：2020-10-01

申请号：US16830313

申请日：2020-03-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

公开(公告)号：US20200227560A1

公开(公告)日：2020-07-16

申请号：US16491248

申请日：2018-03-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshikatsu ITOH ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Masahiko SUZUKI

IPC: H01L29/786 ,  H01L27/12

Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 μm.

公开(公告)号：US20200089037A1

公开(公告)日：2020-03-19

申请号：US16571325

申请日：2019-09-16

Applicant: Sharp Kabushiki Kaisha

Inventor： Hikaru YOSHINO ,  Junichi MORINAGA ,  Tetsuo KIKUCHI ,  Kengo HARA

IPC: G02F1/1333 ,  G02F1/1362 ,  H01L27/12

Abstract: A method for manufacturing an active matrix substrate including a thin film transistor disposed for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: (A) a step of forming an oxide semiconductor layer, a gate insulating layer, and a gate electrode on a substrate; (B) a step of forming an insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, and having a source-side aperture and a drain-side aperture through which portions of the oxide semiconductor layer are exposed; (C) a step of forming a source electrode within the source-side aperture and a drain electrode within the drain-side aperture; (D) a step of forming an interlayer insulating layer including an organic insulating layer and having a first contact hole through which a portion of the drain electrode is exposed; (E) a step of forming a first transparent electrically conductive film on the interlayer insulating layer and within the first contact hole; (F) a step of forming by using a metal film, on a portion of the first transparent electrically conductive film, an upper wiring portion to become an upper layer of the first wiring line; (G) a step of patterning the first transparent electrically conductive film to make a pixel electrode and form a lower wiring portion to become a lower layer of the first wiring line; (H) a step of forming a dielectric layer covering the pixel electrode and the first wiring line and having a second contact hole through which a portion of the first wiring line is exposed; and (I) a step of forming, on the dielectric layer and within the second contact hole, a common electrode which is electrically connected to the first wiring line within the second contact hole. When viewed from a normal direction of the substrate, a bottom face of the first contact hole at least partially overlaps a bottom face of the drain-side aperture, and a bottom face of the second contact hole at least partially overlaps a bottom face of the source-side aperture.

公开(公告)号：US20190148558A1

公开(公告)日：2019-05-16

申请号：US16182643

申请日：2018-11-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L29/1054 ,  H01L29/78648

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

公开(公告)号：US20190103494A1

公开(公告)日：2019-04-04

申请号：US16142082

申请日：2018-09-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/78648 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.

公开(公告)号：US20190097059A1

公开(公告)日：2019-03-28

申请号：US16143528

申请日：2018-09-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  G02F1/1368

Abstract: In a semiconductor device, at least one thin-film transistor includes a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode. The semiconductor layer has a multilayer structure that includes a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer. The first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer. The plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer. The plurality of channel formation layers each have a mobility higher than that of the at least one middle layer.

公开(公告)号：US20180329242A1

公开(公告)日：2018-11-15

申请号：US15776415

申请日：2017-02-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Toshikatsu ITOH ,  Hisao OCHI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Setsuji NISHIMIYA

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1339 ,  G02F1/1333 ,  H01L27/12

CPC classification number: G02F1/1362 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1368 ,  G02F2201/123 ,  H01L27/1214

Abstract: A spacer is fixed while an effect on a surface of an active matrix substrate is prevented. An active matrix substrate (1) includes a thin film transistor (11) which is provided on a substrate (2) and which has a recess made at a surface of the thin film transistor, and a spacer (13) fitted in the recess.