公开(公告)号：US06864536B2

公开(公告)日：2005-03-08

申请号：US09740016

申请日：2000-12-20

Applicant: Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien ,  Wan-Yun Lin

Inventor： Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien ,  Wan-Yun Lin

IPC: H01L27/02 ,  H01L27/12 ,  H01L23/62 ,  H01L29/76

CPC classification number: H01L27/0259 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1087 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

Abstract translation: 静电放电（ESD）保护装置包括半导体层，形成在该层中的源极区，形成在该层中的漏极区，在源极和漏极区之间的层中的沟道区，以及沟道区上的栅极。 多个分流器段分布在漏极区域上并在栅极和漏极触点之间延伸。 段可以由多晶硅或场氧化物形成。

公开(公告)号：US06510088B2

公开(公告)日：2003-01-21

申请号：US09813806

申请日：2001-03-22

Applicant: Wei-Fan Chen ,  Shi-Tron Lin ,  Chen-Hsin Lien

Inventor： Wei-Fan Chen ,  Shi-Tron Lin ,  Chen-Hsin Lien

IPC: G11C700

CPC classification number: G11C11/412

Abstract: The present invention is directed to a semiconductor integrated circuit device having reduced leakage and the method of operating a semiconductor integrated circuit device with reduced leakage. The invention comprises an integrated circuit, including a passing transistor and a bias-application device coupled to the substrate of the passing transistor. The present invention has the passing transistor coupled to a storage cell. The bias-application device applies a first bias voltage of a positive value when the passing transistor is inactivated and applies a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage. Further in accordance with the invention, there is provided a method of reducing the leakage of a passing transistor of N-type. The passing transistor is coupled with a storage cell. The method includes applying a first bias voltage of a positive value when the passing transistor is inactivated, and applying a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage.

公开(公告)号：US06501136B1

公开(公告)日：2002-12-31

申请号：US08931342

申请日：1997-09-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2362

CPC classification number: H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are effectively continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, multiple poly-gate extensions are incorporated to reduce the gate resistance, thereby minimizing the propagation delay of the gate signal.

Abstract translation: 多栅指MOSFET结构将栅极元件定位在漏极和源极扩散区域之间的沟道上，使得整个结构在衬底中的有源区域内。 栅极/沟道到漏极和栅极/沟道到源极扩散边缘沿着栅极/沟道布局是有效连续的，以便在ESD期间级联回跳作用以增强整个栅极元件的均匀导通 事件。 此外，并入多个多栅扩展以减小栅极电阻，从而最小化栅极信号的传播延迟。

公开(公告)号：US06476449B1

公开(公告)日：2002-11-05

申请号：US09946188

申请日：2001-09-05

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2362

CPC classification number: H01L27/0266 ,  H01L21/28518

Abstract: A semiconductor device has a first diffusion region having a silicided portion and a non-silicided portion. The device also has a second diffusion region, and a channel region between the first and second diffusion regions. The non-silicided portion of the first diffusion region has a plurality of non-silicided regions.

Abstract translation: 半导体器件具有具有硅化部分和非硅化部分的第一扩散区域。 该器件还具有第二扩散区域和第一和第二扩散区域之间的沟道区域。 第一扩散区域的非硅化部分具有多个非硅化区域。

公开(公告)号：US06363012B1

公开(公告)日：2002-03-26

申请号：US09472861

申请日：1999-12-27

Applicant: Shi-Tron Lin ,  William W. Y. Lee

Inventor： Shi-Tron Lin ,  William W. Y. Lee

IPC: G11C1604

CPC classification number: G11C16/0416 ,  G11C16/12

Abstract: A method of operating a flash memory structure including a programming step. The method includes providing a flash memory device, the flash memory device comprising a substrate of first conductivity type, a source region of second conductivity type being defined in the substrate and a drain region of second conductivity type defined in the substrate. The flash memory device can be a split gate, a stacked gate, or other type of physical structure. The method includes applying a drain voltage of first polarity type on the drain region and applying a control gate voltage of a first conductivity type on the control gate. The method also includes applying a source voltage of second polarity type ranging from about 0.1 volt to about 0.5 volt on the source region, while maintaining a ground potential on the substrate to inject electrons onto a floating gate to program the floating gate.

Abstract translation: 一种操作包括编程步骤的闪存结构的方法。 该方法包括提供闪速存储器件，闪存器件包括第一导电类型的衬底，在衬底中限定第二导电类型的源极区域和限定在衬底中的第二导电类型的漏极区域。 闪存器件可以是分离栅极，堆叠栅极或其他类型的物理结构。 该方法包括在漏极区域上施加第一极性类型的漏极电压，并在控制栅极上施加第一导电类型的控制栅极电压。 该方法还包括在源极区域上施加范围为约0.1伏特至约0.5伏特的第二极性类型的源极电压，同时在衬底上保持接地电位以将电子注入到浮动栅极上以对浮动栅极进行编程。

公开(公告)号：US06246113B1

公开(公告)日：2001-06-12

申请号：US09154799

申请日：1998-09-17

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2348

CPC classification number: H01L23/60 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be further enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number of consecutively arranged no-connect pins. ESD protection can be provided to any no-connect pin unit on the IC package either by arranging a pair of power pins proximate to the respective sides of the no-connect pin unit; by arranging a power pin proximate to one side of the no-connect pin unit and an elongated conductive tongue proximate to the other side; or by arranging a pair of elongated conductive tongues proximate to the respective sides of the no-connect pin unit. This provides ESD protection to all the no-connect pins in the no-connect pin unit without having to connect them to ESD protection circuits.

Abstract translation: 提供了具有静电放电（ESD）保护功能的IC封装架构，用于IC封装，以便进一步增强IC封装的ESD稳健性，并将其结构复杂性进一步简化为与 现有技术 IC封装包括具有用于在其上安装IC芯片的管芯焊盘的引线框架，具有一些无连接引脚的多个封装引脚，其被组合成至少一个无连接引脚单元，每个单元由一个单独的无连接引脚组成， 连接引脚或多个连续布置的无连接引脚。 可以通过在靠近无连接引脚单元的相应侧面布置一对电源引脚来将ESD保护提供给IC封装上的任何无连接引脚单元; 通过布置靠近所述无连接销单元的一侧的电源销和靠近另一侧的细长导电舌片; 或者通过布置靠近无连接销单元的相应侧面的一对细长导电舌片。 这为无连接引脚单元中的所有无连接引脚提供ESD保护，而无需将其连接到ESD保护电路。

公开(公告)号：US6157070A

公开(公告)日：2000-12-05

申请号：US27533

申请日：1998-02-23

Applicant: Shi-Tron Lin ,  Ta-Lee Yu

Inventor： Shi-Tron Lin ,  Ta-Lee Yu

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/76 ,  H01L27/10 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0921 ,  H01L27/0266

Abstract: In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

Abstract translation: 在多电源CMOS IC中，如果在上电期间VDDH施加得比VDDL慢，则通常反向偏置的一些扩散结可能会瞬间变为正向偏置，并产生闭锁以产生对电路的永久性损坏。 因此，提供了防止在多电源IC中闭锁的保护电路。 保护电路包括一个N沟道MOSFET，其栅极连接到高电压总线，其漏极连接到低压电源，其源极连接到低压母线以控制上电顺序 高电压和低电压的多电源IC，并防止闩锁。 N沟道MOSFET可以具有不同的模式，例如具有低阈值电压的增强模式，耗尽模式或增强模式。

公开(公告)号：US6091593A

公开(公告)日：2000-07-18

申请号：US956271

申请日：1997-10-22

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H02H3/22

CPC classification number: H01L27/0266 ,  H01L27/0251 ,  H01L27/0259

Abstract: A transient voltage pump is provided to generate a negative voltage pulse for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the voltage across the ESD protection device is larger than the trigger voltage of the ESD device while the ESD voltage is still at substantially lower voltage. These negative voltage pulses are used to earlier trigger the NMOS transistor before the ESD transient voltage actually reaches the trigger voltage. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态电压泵以产生用于触发ESD保护装置的导通的负电压脉冲。 由于VDD-VSS电压在初始ESD事件中迅速增加，因此ESD保护器件上的电压大于ESD器件的触发电压，而ESD电压仍处于基本较低的电压。 在ESD瞬变电压实际达到触发电压之前，这些负电压脉冲用于较早触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US06043967A

公开(公告)日：2000-03-28

申请号：US956270

申请日：1997-10-22

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H02H9/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: A transient voltage pump is provided to generate a high voltage pulse for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the voltages of the high voltage pulses are larger than the trigger voltage of the ESD device while the ESD voltage is still at substantially lower voltage. These high voltage pulses are used to early trigger the NMOS transistor before the ESD transient voltage actually reaches the trigger voltage. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态电压泵以产生用于触发ESD保护装置的导通的高电压脉冲。 由于VDD-VSS电压在初始ESD事件中迅速增加，所以高电压脉冲的电压大于ESD器件的触发电压，而ESD电压仍处于基本较低的电压。 这些高电压脉冲用于在ESD瞬态电压实际达到触发电压之前提早触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US5870268A

公开(公告)日：1999-02-09

申请号：US954945

申请日：1997-10-22

Applicant: Shi-Tron Lin ,  Du-Zen Peng ,  Shyh-Chyi Wong

Inventor： Shi-Tron Lin ,  Du-Zen Peng ,  Shyh-Chyi Wong

IPC: H01L27/02 ,  H02H3/22

CPC classification number: H01L27/0251 ,  H01L27/0259 ,  H01L27/0266

Abstract: A transient switching circuit is provided to generate a voltage signal with fast voltage switching phenomenon during the initial ESD transient. The voltage signal is applied to a current spike generator for generating a current spike which forward bias an n+/pwell diode for injecting minority carriers into a substrate on which ESD protection device is embodied. The injected minority carriers are used to trigger turn-on of the ESD protection device. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态开关电路以在初始ESD瞬变期间产生具有快速电压切换现象的电压信号。 电压信号被施加到电流尖峰发生器，用于产生正向偏置n + / pwell二极管的电流尖峰，用于将少数载流子注入到其上体现ESD保护装置的衬底中。 注入的少数载流子用于触发ESD保护装置的导通。 这些少数载流子流向NMOS晶体管的漏极 - 衬底结，使得在比现有技术提供的触发电压低的触发电压下触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。