公开(公告)号：US06473282B1

公开(公告)日：2002-10-29

申请号：US09547186

申请日：2000-04-11

申请人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

发明人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

IPC分类号： H02H320

CPC分类号： H01L27/0251

摘要： A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.

摘要翻译： 公开了一种用于通过第一电力轨道和第二电力轨道供电的集成电路的闩锁保护电路，该集成电路具有至少一个导电类型的半导体本体。 闩锁保护电路包括控制电路和开关电路。 控制电路连接到第一电源轨和第二电源轨，用于检测它们之间的相对电压，并产生第一控制信号和第二控制信号。 开关电路连接到第一电源轨和控制电路。 当相对电压大于第一预定值时，响应于第一控制信号的开关电路将第一电源轨与至少一个半导体块电连接。 当相对电压小于第一预定值时，响应于第一控制信号的开关将第一电力轨与至少一个半导体块电气断开。

公开(公告)号：US5892261A

公开(公告)日：1999-04-06

申请号：US780670

申请日：1997-01-07

申请人： Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

发明人： Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree. bend therein such that a bitline contact in the corresponding corner portion of the active region is located between the bend and an outer peripheral edge of the corner portion. This layout allows the contact-to-diffusion-edge and contact-to-gate-edge spacings of the VDD contacts to be increased such that internal circuit ESD immunity of the memory device is improved without impacting device dimension and layout area constraints.

摘要翻译： 一种在半导体存储器件中使用的装置和方法，用于减少由于位线上拉电路或其它类型电路上的静电放电（ESD）的影响而产生的内部电路损坏。 存储器件中的多个位线中的每一个与相应的N型MOSFET的源极耦合。 每个源极端子形成在存储器件的至少一个有源区域的单独拐角部分中，并且经由布置在拐角部分中的位线接触件耦合到给定的位线。 N型MOSFET的每个漏极端子由有源区域的另一部分形成，并通过VDD触点耦合到存储器件的VDD电源。 给定MOSFET的栅极端子由覆盖有源区域中的沟道的多晶硅栅极区域形成。 栅极区域在其中具有大约90度的弯曲，使得有源区域的相应拐角部分中的位线接触位于弯曲部分和拐角部分的外周边缘之间。 该布局允许增加VDD触点的接触到扩散边缘和接触到栅极边缘间隔，使得存储器件的内部电路ESD抗扰度得到改善，而不会影响器件尺寸和布局面积限制。

公开(公告)号：US06542346B1

公开(公告)日：2003-04-01

申请号：US09586568

申请日：2000-06-02

申请人： Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

发明人： Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

IPC分类号： H02H322

CPC分类号： H01L27/0251 ,  H01L29/7436 ,  H01L29/87

摘要： A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

摘要翻译： 连接到集成电路的焊盘的高压公差输入缓冲器和高压ESD保护电路，用于防止快速栅极氧化物老化。 本发明的高电压公差输入缓冲器包括电压共享电路和开关电路，其中电压共享电路连接在焊盘和电源轨之间，并产生不高于焊盘电压的参考电压 。 开关电路连接到分压电路，并包括控制栅极，以根据参考电压来控制开关电路的开关操作。 本发明可以实现以解决快速栅极氧化物老化问题，而不会通过采用电压共享电路而引起原始工艺流程的任何变化。

公开(公告)号：US6157070A

公开(公告)日：2000-12-05

申请号：US27533

申请日：1998-02-23

申请人： Shi-Tron Lin ,  Ta-Lee Yu

发明人： Shi-Tron Lin ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/76 ,  H01L27/10 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0921 ,  H01L27/0266

摘要： In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

摘要翻译： 在多电源CMOS IC中，如果在上电期间VDDH施加得比VDDL慢，则通常反向偏置的一些扩散结可能会瞬间变为正向偏置，并产生闭锁以产生对电路的永久性损坏。 因此，提供了防止在多电源IC中闭锁的保护电路。 保护电路包括一个N沟道MOSFET，其栅极连接到高电压总线，其漏极连接到低压电源，其源极连接到低压母线以控制上电顺序 高电压和低电压的多电源IC，并防止闩锁。 N沟道MOSFET可以具有不同的模式，例如具有低阈值电压的增强模式，耗尽模式或增强模式。

公开(公告)号：US07012307B2

公开(公告)日：2006-03-14

申请号：US09779096

申请日：2001-02-08

申请人： Shi-Tron Lin ,  Wei-Fan Chen

发明人： Shi-Tron Lin ,  Wei-Fan Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/0251

摘要： An output buffer with a pull down circuit. The pull down circuit is coupled between a second power line and a pad, and has a resistor, a diode and an electrostatic discharge protection component. The resistor deposited on the substrate of a first conductivity type includes a well region of a second conductivity type. The resistor and the electrostatic discharge protection component are connected in series between the pad and the second power line. The diode is formed in the well region, construct by the PN junction formed between a first doped region of the first conductivity type and the well region. The first doped region is electrically floated in the well regions. During an electrostatic discharge event, the pad is instantaneously connected to the first doped region which will help to boost the turn-on of the electrostatic discharge circuit, and further enhance the electrostatic protection effect.

摘要翻译： 具有下拉电路的输出缓冲器。 下拉电路耦合在第二电源线和焊盘之间，并且具有电阻器，二极管和静电放电保护部件。 沉积在第一导电类型的衬底上的电阻器包括第二导电类型的阱区域。 电阻器和静电放电保护元件串联在焊盘和第二电源线之间。 二极管形成在阱区中，由在第一导电类型的第一掺杂区和阱区之间形成的PN结构成。 第一掺杂区域电浮在阱区中。 在静电放电事件期间，焊盘瞬时连接到第一掺杂区域，这有助于提高静电放电电路的接通，并进一步增强静电保护效果。

公开(公告)号：US07009252B2

公开(公告)日：2006-03-07

申请号：US10353372

申请日：2003-01-28

申请人： Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien

发明人： Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien

IPC分类号： H01L26/62

CPC分类号： H01L27/027 ,  H01L27/0203

摘要： ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

公开(公告)号：US06919602B2

公开(公告)日：2005-07-19

申请号：US10320201

申请日：2002-12-16

申请人： Shi-Tron Lin ,  Wei-Fan Chen

发明人： Shi-Tron Lin ,  Wei-Fan Chen

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.

摘要翻译： 门极耦合MOSFET ESD保护电路。 电路具有由逆变器和定时控制电路控制的栅极节点电位。 不同于在ESD事件期间使MOSFET完全导通的电流调节ESD钳位装置，包括下拉元件以形成分压器电路，使得栅极节点电位在一 正静电瞬态事件。 与GCNMOS（栅极耦合NMOS）不同，本发明可以更好地控制瞬态栅极电位，从而在ESD事件期间更有效地触发NMOS进入快速恢复。

公开(公告)号：US06849902B1

公开(公告)日：2005-02-01

申请号：US10796966

申请日：2004-03-11

申请人： Shi-Tron Lin

发明人： Shi-Tron Lin

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device with enhanced ESD robustness. The ESD protection device comprises a pad, a finger-type MOS, a well stripe and a doped segment. The pad is on a semiconductor substrate of a first-conductive type. The finger-type MOS is on the semiconductor substrate and comprises drain regions, source regions and channel regions. Each drain region is of a second-conductive type and is coupled to the pad. Each source region is of the second-conductive type and coupled to a power rail. Channel regions are formed on the semiconductor, substantially parallel to each other. Each channel region is located between one source region and one drain region. The well stripe is of the second-conductive type and formed on the semiconductor, in an angle to the channel regions. The doped segment is of the first-conductive type and in the well stripe. Furthermore, the doped segment is coupled to the pad.

摘要翻译： 具有增强ESD稳健性的静电放电（ESD）保护装置。 ESD保护器件包括焊盘，指状MOS，阱条和掺杂段。 焊盘位于第一导电类型的半导体衬底上。 指状MOS位于半导体衬底上并且包括漏区，源极区和沟道区。 每个漏极区域是第二导电类型并且耦合到该焊盘。 每个源极区域是第二导电类型并且耦合到电力轨道。 通道区域形成在半导体上，基本上彼此平行。 每个沟道区域位于一个源极区域和一个漏极区域之间。 阱条是第二导电类型并且形成在半导体上，与沟道区成一定角度。 掺杂区段是第一导电类型并且在阱条中。 此外，掺杂段耦合到焊盘。

公开(公告)号：US06730967B2

公开(公告)日：2004-05-04

申请号：US09863977

申请日：2001-05-24

申请人： Shi-Tron Lin

发明人： Shi-Tron Lin

IPC分类号： H01L2362

CPC分类号： H01L29/0847 ,  H01L27/0266

摘要： The present invention provides an ESD protection device with isolated islands and an n well. At least one of the isolated islands has an end apart from the boundary of a drain diffusion region of the ESD protection device, to form a gap between. The n well overlaps with the isolated islands and is kept at least a designated distance away from a channel region of the ESD protection device. An interlocked structure of isolated islands is also provided in this invention to direct ESD current flowing forward and backward to the channel region of the ESD protection device, thereby increasing the distributed resistance of the drain diffusion region. Several benefits, such as lower drain capacitance, lower standby power consumption and a wider range of adjustable resistance, are achieved.

摘要翻译： 本发明提供一种具有隔离岛和n阱的ESD保护装置。 隔离岛中的至少一个具有远离ESD保护装置的漏极扩散区域的边界的一端，以在其间形成间隙。 n阱与隔离的岛重叠，并且保持至少距离ESD保护装置的沟道区的指定距离。 本发明还提供隔离岛的互锁结构，以将ESD电流引导到ESD保护器件的沟道区域的前后方向，从而增加漏极扩散区域的分布电阻。 实现了诸如漏极电容降低，待机功耗降低和可调电阻范围更广的好处。

公开(公告)号：US06573568B2

公开(公告)日：2003-06-03

申请号：US09871999

申请日：2001-06-01

申请人： Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien

发明人： Shi-Tron Lin ,  Wei-Fan Chen ,  Chenhsin Lien

IPC分类号： H01L2976

CPC分类号： H01L27/027 ,  H01L27/0203

摘要： ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.