公开(公告)号：US20080071975A1

公开(公告)日：2008-03-20

申请号：US11929810

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080071974A1

公开(公告)日：2008-03-20

申请号：US11929730

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080071931A1

公开(公告)日：2008-03-20

申请号：US11929756

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/38

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US07333364B2

公开(公告)日：2008-02-19

申请号：US11737336

申请日：2007-04-19

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G11C16/06

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634 ,  G11C2211/5641

摘要： A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

摘要翻译： 闪存具有多级单元（MLC），每个单元可以存储多个位。 当发生错误时，单元块可以降级到较少的位/单元，或用于存储关键数据（如引导代码）。 来自单个MLC的位在多个页面之间进行分区，以使用错误校正码（ECC）来提高错误的可校正性。 响应于校准寄存器，由参考电压发生器产生较高的参考电压，校准寄存器可编程为改变上参考电压。 从较高参考电压产生一系列减小的参考值，并将其与位线电压进行比较。 比较结果由翻译逻辑翻译，生成读取数据和编程过程中和编程不足的信号。 降级的单元格使用相同的真值表，但生成较少的读取数据位。 通过使用相同的子状态来读取降级和全密度MLC单元，噪声余量被不对称地改善。

公开(公告)号：US20070283428A1

公开(公告)日：2007-12-06

申请号：US11471000

申请日：2006-09-07

申请人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： H04L9/32

CPC分类号： G06F11/1068 ,  G06F11/1076 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/1545 ,  H03M13/6561

摘要： An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

摘要翻译： 由主机可访问的电子数据闪存卡包括连接到闪速存储器件的闪存控制器和被激活以建立与主机的通信的输入 - 输出接口电路。 在一个实施例中，闪存卡使用USB接口电路与主机进行通信。 闪速存储器控制器包括用于将逻辑地址与物理块地址对准的仲裁器，并且用于执行块管理操作，包括：将重新分配的数据存储到可用块，将过时块中的有效数据重定位到所述可用块并将逻辑块地址重新分配给物理块地址 的所述可用块，找到闪存设备的坏块并用备用块替换，在将有效数据重新定位到可用块之后擦除用于再循环的废弃块，以及擦除块的计数损耗均衡等。此外，每个闪存设备包括 内部缓冲区，用于加快块管理操作。

公开(公告)号：US07953931B2

公开(公告)日：2011-05-31

申请号：US12035398

申请日：2008-02-21

申请人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/12

CPC分类号： G06F13/161 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/123 ,  G06F2212/7203 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641 ,  G11C2211/5643

摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

公开(公告)号：US20110093653A1

公开(公告)日：2011-04-21

申请号：US12980591

申请日：2010-12-29

申请人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： H05K1/182 ,  G06F12/00 ,  H01R13/447 ,  H05K1/181 ,  H05K5/0278 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1572

摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

公开(公告)号：US07827348B2

公开(公告)日：2010-11-02

申请号：US12017249

申请日：2008-01-21

申请人： Charles C. Lee ,  I-Kang Yu ,  David Q. Chow ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  David Q. Chow ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F11/1068 ,  G11C5/04

摘要： High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.

摘要翻译： 描述了高性能闪存设备（FMD）。 根据本发明的一个示例性实施例，高性能FMD包括I / O接口，FMD控制器以及至少一个非易失性存储器模块以及对应的至少一个通道控制器。 I / O接口被配置为将高性能FMD连接到主机计算设备FMD控制器被配置为控制主计算设备和主计算设备之间的数据传输（例如，数据读取，数据写入/编程和数据擦除）操作 非易失性内存模块。 包括一个或多个非易失性存储器芯片的至少一个非易失性存储器模块被配置为主计算设备的辅助存储器。 至少一个通道控制器被配置为确保位于FMD控制器和至少一个非易失性存储器模块中的一组数据缓冲器之间的适当和有效的数据传输。

公开(公告)号：US20080195798A1

公开(公告)日：2008-08-14

申请号：US11932941

申请日：2007-10-31

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham Chih-Kang Ma ,  I-Kang Yu ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham Chih-Kang Ma ,  I-Kang Yu ,  Ming-Shiang Shen

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1416 ,  G06F3/0664 ,  G06F3/0688 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.

摘要翻译： 描述了基于非易失性存储器的计算机系统和方法。 根据本发明的一个方面，至少一个非易失性存储器模块耦合到作为主存储器的计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为主存储器的北桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置为与计算机系统的微处理器相关联的高速缓存行之一的大小。 根据另一方面，至少一个非易失性存储器模块作为一个或多个硬盘驱动器的数据读/写缓冲器耦合到计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为输入/输出设备的南桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置成与硬盘驱动器的特性成比例。

公开(公告)号：US20080192928A1

公开(公告)日：2008-08-14

申请号：US11924448

申请日：2007-10-25

申请人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： H04L9/28 ,  H04L9/00 ,  G06F12/14

CPC分类号： G06F12/1416 ,  G06F21/78 ,  G06F21/85 ,  G06F2221/2107 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087 ,  H04L9/0631 ,  H04L9/0894 ,  H04L9/3228 ,  H04L2209/34

摘要： Portable electronic storage devices with hardware based security are described. According to one exemplary embodiment of the present invention, a portable electronic storage device (PESD) comprises a security engine integrated thereon. The security engine is configured to provide data encryption, data decryption, and encryption/decryption key (referred to as a key) generation according to a security standard (e.g., Advance Encryption Standard (AES)). AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit data block is encrypted by transforming the data block in a unique way into a new data block of the same size. AES is symmetric sine the same key is used for encryption and the reverse transformation (i.e., decryption). The only secret necessary to keep for security is the key. AES may use different key-lengths (i.e., 128-bit, 192-bits and 256-bits).

摘要翻译： 描述了具有硬件安全性的便携式电子存储设备。 根据本发明的一个示例性实施例，便携式电子存储设备（PESD）包括集成在其上的安全引擎。 安全引擎被配置为根据安全标准（例如，高级加密标准（AES））提供数据加密，数据解密和加密/解密密钥（称为密钥）生成。 AES是一种对称加密算法，处理128位数据块。 在密钥的影响下，通过以独特的方式将数据块变换成相同大小的新数据块来加密128位数据块。 AES是对称正弦，相同的密钥用于加密和反向转换（即解密）。 保护安全所必需的唯一秘密就是关键。 AES可以使用不同的密钥长度（即128位，192位和256位）。