公开(公告)号：US20180040482A1

公开(公告)日：2018-02-08

申请号：US15594883

申请日：2017-05-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/772 ,  H01L21/306 ,  G11C16/04

CPC classification number: H01L21/28 ,  G11C16/0425 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/772

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

公开(公告)号：US09659946B2

公开(公告)日：2017-05-23

申请号：US15287672

申请日：2016-10-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

公开(公告)号：US09634018B2

公开(公告)日：2017-04-25

申请号：US15050309

申请日：2016-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L29/788 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/105 ,  H01L27/11551

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US09496369B2

公开(公告)日：2016-11-15

申请号：US15002307

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Chun-Ming Chen ,  Nhan Do

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

公开(公告)号：US09484261B2

公开(公告)日：2016-11-01

申请号：US14319893

申请日：2014-06-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

公开(公告)号：US20160276357A1

公开(公告)日：2016-09-22

申请号：US15050309

申请日：2016-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：US20160260728A1

公开(公告)日：2016-09-08

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract translation: 一种存储器件和方法，包括具有存储器和逻辑器件区域的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 形成在逻辑器件区域中的多个逻辑器件，每个逻辑器件包括在其间具有第二沟道区域的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。

公开(公告)号：US20160218195A1

公开(公告)日：2016-07-28

申请号：US15002307

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Chun-Ming Chen ,  Nhan Do

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

公开(公告)号：US09123822B2

公开(公告)日：2015-09-01

申请号：US13958483

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

公开(公告)号：US20150206788A1

公开(公告)日：2015-07-23

申请号：US14162309

申请日：2014-01-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Wang ,  Chien-Sheng Su

IPC: H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。