公开(公告)号：US20210407602A1

公开(公告)日：2021-12-30

申请号：US16915289

申请日：2020-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

公开(公告)号：US20140104961A1

公开(公告)日：2014-04-17

申请号：US13466878

申请日：2012-05-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract translation: 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。

公开(公告)号：US12014793B2

公开(公告)日：2024-06-18

申请号：US17858185

申请日：2022-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/50

CPC classification number: G11C29/50016 ,  G11C16/14 ,  G11C16/26 ,  G11C16/349 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.

公开(公告)号：US11309042B2

公开(公告)日：2022-04-19

申请号：US16915289

申请日：2020-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

公开(公告)号：US10991433B2

公开(公告)日：2021-04-27

申请号：US16803418

申请日：2020-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/16 ,  G11C16/26

Abstract: A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substantially 10 seconds of their erasure, erases the first group, and programs the first group within substantially 10 seconds of their erasure. In response to a second command for erasing and programming a second group of the memory cells, the controller determines that the second group cannot be programmed within substantially 10 seconds of their erasure, divides the second group into subgroups of the memory cells each of which can be programmed within substantially 10 seconds of their erasure, and for each of the subgroups, erase the subgroup and program the subgroup within substantially 10 seconds of their erasure.

公开(公告)号：US20160336072A1

公开(公告)日：2016-11-17

申请号：US15084955

申请日：2016-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Viktor Markov ,  Jong-Won Yoo ,  Xiao Yan Pi ,  Alexander Kotov

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0425 ,  G11C16/10

Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

Abstract translation: 所公开的实施例包括闪存器件和以与现有技术方法相比降低器件劣化的方式对器件进行编程的方法。

公开(公告)号：US20150035040A1

公开(公告)日：2015-02-05

申请号：US13958483

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

公开(公告)号：US12080355B2

公开(公告)日：2024-09-03

申请号：US17481225

申请日：2021-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0425 ,  G11C16/14 ,  G11C16/3431

Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

公开(公告)号：US11769558B2

公开(公告)日：2023-09-26

申请号：US17482095

申请日：2021-09-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2216/04

Abstract: A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the method includes programming each of the non-volatile memory cells in the memory cell group to a particular program state, performing multiple read operations on each of the non-volatile memory cells in the memory cell group, identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and programming the identified non-volatile memory cell in the memory cell group with user data.

公开(公告)号：US11205490B2

公开(公告)日：2021-12-21

申请号：US16828206

申请日：2020-03-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/16 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/28 ,  G11C29/50 ,  G11C16/34 ,  G11C29/04 ,  G11C29/44

Abstract: A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.