公开(公告)号：US20100156460A1

公开(公告)日：2010-06-24

申请号：US12717315

申请日：2010-03-04

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/17728

Abstract: A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

Abstract translation: 逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。 时钟复用器具有耦合到时钟资源的输入和输出。 输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。 触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。 逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。 触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

公开(公告)号：US07701250B1

公开(公告)日：2010-04-20

申请号：US12360971

申请日：2009-01-28

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/17728

Abstract: A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

Abstract translation: 逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。 时钟复用器具有耦合到时钟资源的输入和输出。 输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。 触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。 逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。 触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

公开(公告)号：US07545169B1

公开(公告)日：2009-06-09

申请号：US12173225

申请日：2008-07-15

Applicant: Wenyi Feng ,  Sinan Kaptanoglu

Inventor： Wenyi Feng ,  Sinan Kaptanoglu

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.

Abstract translation: 用于可编程逻辑器件的互连架构包括多个互连路由线。 多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。 多个第二级多路复用器被组织成多路复用器组。 多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。 每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。 第二级复用器的数据输入连接到第一级复用器的输出，使得每个第一级多路复用器的每个输出连接到每个多路复用器组中仅一个第二级多路复用器的输入。

公开(公告)号：US20080204074A1

公开(公告)日：2008-08-28

申请号：US12114143

申请日：2008-05-02

Applicant: King W. Chan ,  William C.T. Shu ,  Sinan Kaptanoglu ,  Chi Fung Cheng

Inventor： King W. Chan ,  William C.T. Shu ,  Sinan Kaptanoglu ,  Chi Fung Cheng

IPC: H03K19/177

CPC classification number: H03K19/177 ,  G06F15/7867

Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Abstract translation: 用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

公开(公告)号：US20080136449A1

公开(公告)日：2008-06-12

申请号：US12069830

申请日：2008-02-12

Applicant: Michael Hutton ,  Sinan Kaptanoglu

Inventor： Michael Hutton ,  Sinan Kaptanoglu

IPC: H03K19/173 ,  G06F7/00

CPC classification number: H03K19/17736 ,  G06F5/01

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

公开(公告)号：US20080136446A1

公开(公告)日：2008-06-12

申请号：US12034555

申请日：2008-02-20

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H01L27/11803

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy is are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Board (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.

Abstract translation: FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中层层次中的路由资源是包括互连导体组的高速公路路由信道M 1，M 2和M 3。 在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。 每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M 1，M 2和M 3提供每个B1块的接入。 每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。 每组三个互连导体连接到扩展板（EB）3x3开关矩阵的第一侧。 每个EB 3x3开关矩阵的第二面耦合到E-tab。 在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

公开(公告)号：US07385421B2

公开(公告)日：2008-06-10

申请号：US11748865

申请日：2007-05-15

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17796

Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

Abstract translation: FPGA架构具有顶级，中级和低级。 顶级是由I / O块包围的B16x16瓦数组。 中间路由资源是高速公路路由信道，包括互连导体。 在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。 每个B 1块包括四组设备。 每个簇包括第一和第二LUT 3 s，LUT 2和DFF。 LUT 3中的每一个具有三个输入和一个输出。 LUT 2中的每一个具有两个输入和一个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT 3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

公开(公告)号：US20070285126A1

公开(公告)日：2007-12-13

申请号：US11843575

申请日：2007-08-22

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.

Abstract translation: 一种用于在现场可编程门阵列中路由信道的转动结构，包括具有第一方向的第一多个路由信道和具有第二方向的第二多个路由信道。 第一多个路由信道与第二多个路由信道相交，以在路由信道中形成多个交叉互连导体矩阵。 第一数量的可编程元件设置在多个矩阵中的至少一个矩阵中的交点处，第二数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第二数量的可再编程元件大于第一数量的可再编程元件，并且第三数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第三数量的可编程元件大于第二数量的可编程元件。

公开(公告)号：US07279930B2

公开(公告)日：2007-10-09

申请号：US11202686

申请日：2005-08-12

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.

Abstract translation: 一种用于在现场可编程门阵列中路由信道的转动结构，包括具有第一方向的第一多个路由信道和具有第二方向的第二多个路由信道。 第一多个路由信道与第二多个路由信道相交，以在路由信道中形成多个交叉互连导体矩阵。 第一数量的可编程元件设置在多个矩阵中的至少一个矩阵中的交点处，第二数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第二数量的可再编程元件大于第一数量的可再编程元件，并且第三数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第三数量的可编程元件大于第二数量的可编程元件。

公开(公告)号：US20070210829A1

公开(公告)日：2007-09-13

申请号：US11748865

申请日：2007-05-15

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17796

Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

Abstract translation: FPGA架构具有顶级，中级和低级。 顶级是由I / O块包围的B16x16瓦数组。 中间路由资源是高速公路路由信道，包括互连导体。 在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。 每个B 1块包括四组设备。 每个簇包括第一和第二LUT 3 s，LUT 2和DFF。 LUT 3中的每一个具有三个输入和一个输出。 LUT 2中的每一个具有两个输入和一个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT 3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。