公开(公告)号：US07898306B1

公开(公告)日：2011-03-01

申请号：US12235507

申请日：2008-09-22

申请人： Chi Fung Cheng

发明人： Chi Fung Cheng

IPC分类号： H03L7/16

CPC分类号： H03L7/081

摘要： A phase locked loop (PLL) is provided. In one implementation, the PLL includes a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals, a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal, and a fractional divider to fractionally divide an input phase signal. The fractional divider can include an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, to produce an interpolated output signal having a desired frequency resolution.

摘要翻译： 提供锁相环（PLL）。 在一个实现中，PLL包括可操作以产生包含一个或多个相位信号的输出信号的多相压控振荡器（VCO），可编程分频器，可操作以分频多相VCO的输出信号的频率以产生分频输出 信号和一个分数分频器来对输入相位信号进行分数分频。 分数除法器可以包括一个整数除法器，可操作用于接收输入相位信号，并根据整数除数分频输入相位信号，以产生分频信号作为多相VCO的输入;以及相位插值器，可操作以选择相位信号 从由多相VCO输出的一个或多个相位信号中产生具有期望频率分辨率的内插输出信号。

公开(公告)号：US07825737B1

公开(公告)日：2010-11-02

申请号：US12334701

申请日：2008-12-15

申请人： Steve Fang ,  Chi Fung Cheng

发明人： Steve Fang ,  Chi Fung Cheng

IPC分类号： H03L7/087

CPC分类号： H03L7/081 ,  H03L7/085 ,  H03L7/087

摘要： A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

摘要翻译： 频率锁相环（FPLL）包括耦合到第二反馈环路的第一反馈环路。 第一个反馈回路被配置为校正FPLL的输出信号的相位偏移。 第二反馈回路被配置为校正FPLL的输出信号的频率偏移。

公开(公告)号：US07589649B1

公开(公告)日：2009-09-15

申请号：US11800554

申请日：2007-05-04

申请人： Arshan Aga ,  Chi Fung Cheng ,  Hongxin Song

发明人： Arshan Aga ,  Chi Fung Cheng ,  Hongxin Song

IPC分类号： H03M1/06

CPC分类号： H03M1/1295 ,  G11B7/005

摘要： Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.

摘要翻译： 用于补偿模拟存储设备的读通道中的基线偏移的装置，方法和系统。 该装置通常包括被配置为将模拟信号从模拟存储设备传送到读通道的AC耦合电路，耦合到AC耦合电路的可配置电流器件，耦合到AC耦合电路的比较器，以及耦合到 所述可配置电流装置和所述比较器，其中所述逻辑适于响应于所述AC耦合电路和所述比较器中的至少一个的输出来配置所述当前装置。 该方法通常包括以下步骤：将模拟存储设备和读取通道与AC耦合电路耦合，检测AC耦合电路下游节点处的模拟信号的基线或分量，并将当前设备配置为 响应于检测到模拟信号的基线或分量来修改模拟信号，其中当前设备耦合到从AC耦合电路下游的节点并且被配置为对模拟信号进行操作的信号处理器的上游。

公开(公告)号：US06721114B1

公开(公告)日：2004-04-13

申请号：US09874949

申请日：2001-06-05

申请人： Pantas Sutardja ,  Chi Fung Cheng

发明人： Pantas Sutardja ,  Chi Fung Cheng

IPC分类号： G11B509

CPC分类号： G11B20/10194 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403 ,  G11B2005/001

摘要： In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.

摘要翻译： 在用于数据信号的磁记录的预补偿电路中，时钟以预定速率产生时钟信号以对数据信号的记录进行时钟。 时钟延迟发生器相对于所记录的连续数据信号产生的时钟信号产生时钟延迟数据。 根据一组相邻数据信号的状态，形成每个数据信号的时钟延迟数据。 n> 1个可编程时钟延迟单元依次操作以控制连续数据信号的记录时间。 每个时钟延迟单元在n个连续数据信号的每个序列中接收一个数据信号的时钟延迟数据，并根据序列中的一个数据信号的时钟延迟数据确定一个数据信号的记录时间。

公开(公告)号：US08990757B2

公开(公告)日：2015-03-24

申请号：US12114143

申请日：2008-05-02

申请人： King W. Chan ,  William C. T. Shu ,  Sinan Kaptanoglu ,  Chi Fung Cheng

发明人： King W. Chan ,  William C. T. Shu ,  Sinan Kaptanoglu ,  Chi Fung Cheng

IPC分类号： G06F17/50 ,  H03K19/177 ,  G06F15/78

CPC分类号： H03K19/177 ,  G06F15/7867

摘要： An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

摘要翻译： 用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

公开(公告)号：US08358478B1

公开(公告)日：2013-01-22

申请号：US13012422

申请日：2011-01-24

申请人： Chi Fung Cheng

发明人： Chi Fung Cheng

IPC分类号： G11B5/02

CPC分类号： G11B5/09 ,  G11B20/10194 ,  G11B20/10222 ,  G11B2220/2516

摘要： A device is provided that, in one implementation, includes interpolators to generate interpolated phase shifted signals, and a precompensation circuit to provide precompensated versions of data bits in accordance with the interpolated phase shifted signals. Each of the interpolators is assigned a bit pattern different from that assigned to remaining ones of the interpolators.

摘要翻译： 提供了一种装置，其在一个实现中包括内插器以产生内插相移信号，以及预补偿电路，以根据内插相移信号提供预补偿版本的数据位。 每个内插器被分配与分配给剩余的内插器的位模式不同的位模式。

公开(公告)号：US07583459B1

公开(公告)日：2009-09-01

申请号：US10993106

申请日：2004-11-18

申请人： Chi Fung Cheng

发明人： Chi Fung Cheng

IPC分类号： G11B5/09

CPC分类号： G11B5/09 ,  G11B20/10194 ,  G11B20/10222 ,  G11B2220/2516

摘要： A phase interpolator is provided that, in one implementation, includes an output node, a plurality of phase input circuits, and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit is operable to receive a given phase signal. Each switch is in communication with a given phase input circuit and is operable to couple a given phase signal to the output node.

摘要翻译： 提供了一种相位插值器，其在一个实现中包括输出节点，多个相位输入电路和对应于多个相位输入电路的多个开关。 每相输入电路可操作以接收给定的相位信号。 每个开关与给定的相位输入电路通信，并且可操作以将给定的相位信号耦合到输出节点。

公开(公告)号：US07161752B1

公开(公告)日：2007-01-09

申请号：US10701491

申请日：2003-11-05

申请人： Chi Fung Cheng

发明人： Chi Fung Cheng

IPC分类号： G11B5/09 ,  G11B5/02

CPC分类号： H03F3/45475 ,  G11B2005/0018 ,  H03F3/45183 ,  H03F2203/45068 ,  H03F2203/45418 ,  H03F2203/45652 ,  H03F2203/45726

摘要： An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.

摘要翻译： 一种用于在HDD系统中使用磁阻（MR）头提供不对称信号校正的装置，方法和系统，用于读取存储在其上的信息。 MR磁头产生不对称的信号，而非对称校正电路校正不对称信号进行进一步处理。 非对称校正电路包括具有可变增益的差分放大器，用于产生与非对称信号成比例的电流。 差分放大器与两个高速开关耦合，用于产生仅具有正极性的输出信号。 当非对称校正输出信号与输入信号组合时，所得到的信号近似于非对称输入信号的反向失真。

公开(公告)号：US06429987B1

公开(公告)日：2002-08-06

申请号：US09546039

申请日：2000-04-10

申请人： Chi Fung Cheng

发明人： Chi Fung Cheng

IPC分类号： G11B509

CPC分类号： G11B5/022 ,  G11B5/02 ,  G11B2005/0013 ,  H03K17/04163 ,  H03K17/162 ,  H03K17/6872

摘要： A high speed write driver for an inductive head of a magnetic storage medium is provided which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. An input voltage control stage controls a voltage applied to the inductive head from the voltage source. A current supply to supplies current to the inductive head element, and a damping circuit in communication with the inductive head element. An overshoot suppressor circuit is provided such that the input voltage control tage is responsive to the overshoot suppressor circuit.

摘要翻译： 提供了一种用于磁存储介质的感应头的高速写入驱动器，其包含用于减小电感头电流过冲的机构，从而减少抖动并因此减小写周期频率。 输入电压控制级控制从电压源施加到感应头的电压。 用于向感应头元件供电的电流源，以及与感应头元件连通的阻尼电路。 提供过冲抑制电路，使得输入电压控制量程对过冲抑制电路做出响应。

公开(公告)号：US08427353B2

公开(公告)日：2013-04-23

申请号：US13027625

申请日：2011-02-15

申请人： Lawrence Chi Fung Cheng

发明人： Lawrence Chi Fung Cheng

IPC分类号： H03M1/36

CPC分类号： H03M1/06 ,  H03M1/361

摘要： Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.

摘要翻译： 公开了具有线性电压梯度的至少一个闪存模数转换器实施例，一组比较器，每个比较器通过采样开关耦合到一个或多个运算放大器。 每个采样开关对比较器输出进行采样，使用运算放大器的寄生电容来保持电压。 采样开关可以是单个晶体管。 一些实施例还包括每个比较器多个运算放大器，每个运算放大器经由门控开关驱动二进制锁存器。 门控开关按顺序操作，以将顺序样本分配到不同的锁存器。 闪存转换器的至少一些实施例还包括具有差分输入端和差分输出端两者的自动增益控制（AGC）。 在这样的实施例中，比较器将AGC的差分输出与差分参考电压进行比较，并且还可以将结果作为差分信号提供。