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    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask
    41.
    发明授权
    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask 有权
    通过氮化物硬掩模层和氧化物掩模形成沟道半导体合金

    公开(公告)号：US08673710B2

    公开(公告)日：2014-03-18

    申请号：US13197387

    申请日：2011-08-03

    申请人： Stephan Kronholz ,  Rohit Pal

    发明人： Stephan Kronholz ,  Rohit Pal

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

    摘要翻译： 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
    43.
    发明授权
    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices 有权
    在密集封装的半导体器件中，在沟槽隔离结构中埋设蚀刻停止层以获得出色的表面平面度

    公开(公告)号：US08334573B2

    公开(公告)日：2012-12-18

    申请号：US12858727

    申请日：2010-08-18

    申请人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    发明人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    IPC分类号： H01L27/088

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

    摘要翻译： 先进的半导体器件中的沟槽隔离结构的材料侵蚀可以通过在早期制造阶段中合并适当的掩模层堆叠来减少。 例如，氮化硅材料可以在用于图案化有源区域并在其中形成应变诱导半导体合金的序列之前作为掩埋蚀刻停止层引入，其中特别地，在选择性外延生长工艺之前的相应的清洁工艺 已经被确定为在沉积层间介电材料时引起沉积相关不规则的主要来源。

    EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER
    45.
    发明申请
    EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER 有权
    早期嵌入式硅锗，含有硼酸盐和氧化物/硝酸盐邻近间隔物

    公开(公告)号：US20120267683A1

    公开(公告)日：2012-10-25

    申请号：US13089799

    申请日：2011-04-19

    申请人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    发明人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  B82Y99/00 ,  B82Y40/00

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.

    摘要翻译： 在形成eSiGe间隔物之前，器件由氧化物衬垫和氮化物层形成。 实施例包括在衬底上形成第一和第二栅极堆叠，在第一和第二栅极堆叠上形成氧化物衬垫，在氧化物衬底上形成氮化物层，在第一栅极堆叠上形成抗蚀剂，在氮化物层上形成氮化物间隔物， 形成用于第二栅极堆叠的eSiGe源极/漏极区域，随后形成用于第一栅极堆叠的卤素/延伸区域，并且独立地形成用于第二栅极叠层的卤素/延伸区域。 实施例包括通过使用氮化物间隔物作为软掩模，用TMAH湿蚀刻衬底来形成eSiGe区域，形成σ形空腔，以及在空腔中外延生长的硼掺杂eSiGe。

    Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures
    50.
    发明申请
    Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures 有权
    用于控制包含高K金属栅电极结构的晶体管中半导体合金的引入的测试结构

    公开(公告)号：US20120001174A1

    公开(公告)日：2012-01-05

    申请号：US12965341

    申请日：2010-12-10

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    IPC分类号： H01L23/544 ,  H01L21/66

    CPC分类号： H01L22/12 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.

    摘要翻译： 当在复杂的半导体器件中形成临界阈值调节半导体合金和/或应变诱导嵌入式半导体材料时，可以通过提供适当设计的测试结构，基于机械收集的轮廓测量数据来有效地监测至少相应的蚀刻工艺。 因此，可以通过机械获得的轮廓测量数据有效地监视和/或控制在体半导体器件上执行的复杂工艺序列而没有显着的延迟。 例如，可以实现在用于非SOI器件的复杂高k金属栅极电极结构中提供阈值调节半导体合金时的均匀性。