公开(公告)号：US06366132B1

公开(公告)日：2002-04-02

申请号：US09474881

申请日：1999-12-29

申请人： Tanay Karnik ,  Ram K. Krishnamurthy

发明人： Tanay Karnik ,  Ram K. Krishnamurthy

IPC分类号： H03K19096

CPC分类号： H03K3/356156 ,  H03K3/356165

摘要： In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node. In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes. In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.

摘要翻译： 在一些实施例中，本发明包括一个软错误锁存电路。 锁存电路包括存储节点，反馈节点和存储节点与反馈节点之间的逆变器。 锁存电路还包括分离连接存储节点驱动器和分离连接反馈节点驱动器，每个驱动器连接到存储节点和反馈节点。 在一些实施例中，本发明包括一个防错误的多米诺骨牌电路，一个多米诺骨牌节点，一个守门员节点和一个防错误的门禁器。 软误差保护器包括（a）具有连接到保持器节点的栅极的FET; （b）具有连接到多米诺骨牌节点的门的FET; 和（c）多米诺骨牌和守门员节点之间的逆变器。 在一些实施例中，本发明包括具有多米诺骨牌节点，守门员节点以及多米诺骨牌和守门员节点之间的逆变器的防错误的多米诺骨牌电路。 电路还包括连接在多米诺骨牌节点和守门员节点之间的反向连接保持器驱动程序。

公开(公告)号：US06225826B1

公开(公告)日：2001-05-01

申请号：US09220816

申请日：1998-12-23

申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath ,  Mark A. Anders

发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath ,  Mark A. Anders

IPC分类号： H03K19096

CPC分类号： H03K19/096 ,  H03K19/0963

摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.

摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。

公开(公告)号：US09262256B2

公开(公告)日：2016-02-16

申请号：US14140243

申请日：2013-12-24

申请人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

发明人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

IPC分类号： G06F21/00 ,  H04L29/06 ,  G06F11/07 ,  G11C7/24 ,  G11C7/00 ,  G06F7/58 ,  H04L9/34

CPC分类号： G06F11/0793 ,  G06F7/00 ,  G06F7/588 ,  G06F11/0745 ,  G11C7/24 ,  H04L9/3278 ,  H04L9/34

摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

摘要翻译： 描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。 计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。 安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。 暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。 暗位表示PUF组件的PUF值在暗位窗口期间不稳定。 当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为 黑暗的一点

公开(公告)号：US20150220470A1

公开(公告)日：2015-08-06

申请号：US14126910

申请日：2013-06-28

申请人： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

发明人： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/4282 ,  G06F15/7825 ,  H04L12/46 ,  H04L49/109 ,  H04L67/10 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。 描述和要求保护其他实施例。

公开(公告)号：US20150023500A1

公开(公告)日：2015-01-22

申请号：US14507427

申请日：2014-10-06

申请人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

发明人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

IPC分类号： H04L9/08

CPC分类号： H04L9/0861 ,  H04L9/0618 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/0816 ,  H04L2209/125 ,  H04L2209/24 ,  H04N1/32277

摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.

摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

公开(公告)号：US06838910B2

公开(公告)日：2005-01-04

申请号：US10633127

申请日：2003-08-01

申请人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

发明人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

IPC分类号： H03K3/356 ,  H03K19/096

CPC分类号： H03K3/356113 ,  H03K3/356173

摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

摘要翻译： 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。 交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。

公开(公告)号：US06791364B2

公开(公告)日：2004-09-14

申请号：US09896252

申请日：2001-06-28

申请人： Atila Alvandpour ,  Ram K. Krishnamurthy

发明人： Atila Alvandpour ,  Ram K. Krishnamurthy

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  G01R31/2855

摘要： A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

摘要翻译： 具有用于老化的条件保持器的动态电路。 在所描述的实施例中，提供了仅在老化测试期间有效的条件保持器，其中条件保持器的尺寸大于标准保持器，以便补偿动态电路中的附加泄漏电流。

公开(公告)号：US06717441B2

公开(公告)日：2004-04-06

申请号：US10021544

申请日：2001-10-22

申请人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

发明人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

IPC分类号： H03K19096

CPC分类号： H03K3/356113 ,  H03K3/356173

摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

摘要翻译： 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。 交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。

公开(公告)号：US06519178B2

公开(公告)日：2003-02-11

申请号：US10172107

申请日：2002-06-13

申请人： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

发明人： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

IPC分类号： G11C1140

CPC分类号： G11C11/412

摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

公开(公告)号：US06181166B2

公开(公告)日：2001-01-30

申请号：US09099993

申请日：1998-06-19

申请人： Ram K. Krishnamurthy ,  Soumyanath Krishnamurthy

发明人： Ram K. Krishnamurthy ,  Soumyanath Krishnamurthy

IPC分类号： H03K190175

CPC分类号： H03K19/018507 ,  H03K5/151 ,  H03K19/09429

摘要： A signal driver circuit uses a single power supply to provide differential low voltage swing signals for use in an integrated circuit. The driver reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect. The driver includes series coupled drive transistors to provide differential signals on integrated circuit interconnects. The driver circuit can include circuitry to place the interconnects in a tri-state condition to allow for shared interconnects. An integrated circuit, such as a processor, includes first and second differential interconnects, a receiver circuit connected to the first and second differential interconnects for detecting a differential voltage provided thereon, and a driver circuit connected to the first and second differential interconnects for providing the differential voltage.

摘要翻译： 信号驱动器电路使用单个电源来提供用于集成电路的差分低电压摆幅信号。 驱动器降低互连电压摆幅和功耗，同时提高互连的速度性能。 驱动器包括串联耦合的驱动晶体管，以在集成电路互连上提供差分信号。 驱动器电路可以包括将互连置于三态条件以允许共享互连的电路。 诸如处理器的集成电路包括第一和第二差分互连，连接到第一和第二差分互连用于检测其上提供的差分电压的接收器电路，以及连接到第一和第二差分互连的驱动器电路，用于提供 差分电压。