公开(公告)号：US20070124463A1

公开(公告)日：2007-05-31

申请号：US11627887

申请日：2007-01-26

Applicant: Shreedhar Madhavapeddi ,  Rajesh Sundaram ,  Eric Eilebrecht

Inventor： Shreedhar Madhavapeddi ,  Rajesh Sundaram ,  Eric Eilebrecht

IPC: G06F15/173

CPC classification number: H04L67/322

Abstract: Methods and computer program products are disclosed for providing QoS for Web applications via an internet service application programming interface “ISAPI”) filter running on an internet information server, wherein the ISAPI filter uses a traffic control application programming interface to manage bandwidth for individual HTTP requests. Responses to HTTP requests can be prioritized based on policies defined by the Web application developer, wherein policy decisions may be made based on many different parameters, such as, for example, the IP address of the Web browser making the request, the type of browser being used, HTTP “cookies,” the uniform resource locator being requested, an authenticated user ID, or any other information that is exposed from the Internet information server through server variables. The present invention accomplishes this with no modifications to the internet information server, and with very minimal changes to the Web application.

Abstract translation: 公开了用于通过互联网信息服务器上运行的因特网服务应用程序编程接口“ISAPI”）过滤器为Web应用程序提供QoS的方法和计算机程序产品，其中ISAPI过滤器使用流量控制应用编程接口来管理各个HTTP请求的带宽 。 基于Web应用程序开发人员定义的策略可以对HTTP请求的响应进行优先级排序，其中策略决定可以基于许多不同的参数进行，例如，提供请求的Web浏览器的IP地址，浏览器的类型 正在使用的HTTP“cookies”，正在请求的统一资源定位符，经过身份验证的用户ID或通过服务器变量从Internet信息服务器公开的任何其他信息。 本发明不对互联网信息服务器进行修改，并且对Web应用程序进行极小的改变。

公开(公告)号：US07093044B2

公开(公告)日：2006-08-15

申请号：US10971031

申请日：2004-10-25

Applicant: Joseph M Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

Inventor： Joseph M Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

IPC: G06F13/00

CPC classification number: H04L12/40058 ,  H04L12/40065 ,  H04L47/13 ,  H04L49/205

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits using the allocated isochronous channel. In a third variation, multiple receiving nodes that need to receive streaming data from a single transmitting node share a common isochronous data channel. In any of these variations, each receiver can periodically transmit a “deadman” timer message on a broadcast channel to indicate that it is still receiving on a given channel. If a transmitter detects that the deadman timer has expired, it reverts to transmitting data using a “best-efforts” scheme. A transmitter can transmit both to receivers that can handle QoS services and those that cannot explicitly support QoS services.

Abstract translation: 本发明通过具有同步数据传输能力的计算机总线提供服务质量（QoS）传递服务。 总线上的发送节点向指定的接收者发送指示所请求的连接带宽的消息。 如果预期的接收者有足够的资源，它将在总线上分配一个同步数据信道，并向发射机通知所分配的信道。 此后，发射机在分配的信道上发送数据。 如果接收者不能分配信道，则它不响应，并且发射机此后检测到超时条件，并且使用“尽力而为”的方案开始发送（即，非保证的时间传递）。 在第二变体中，接收节点检测到它正在从发送节点接收大量的数据。 作为响应，接收节点在总线上分配等时数据信道，并向发射机通知所分配的信道。 此后，发射机使用所分配的同步信道进行发射。 在第三变型中，需要从单个发射节点接收流数据的多个接收节点共享公共同步数据信道。 在这些变型中的任何一个中，每个接收机可以在广播信道上周期性地发送“死机”定时器消息，以指示它仍然在给定信道上接收。 如果发射机检测到死机定时器已经过期，则它将恢复为使用“尽力而为”方案发送数据。 发射机可以将两者传输到可以处理QoS服务的接收机和不能明确支持QoS服务的接收机。

公开(公告)号：US06952797B1

公开(公告)日：2005-10-04

申请号：US09696666

申请日：2000-10-25

Applicant: Andy Kahn ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Steven R. Kleiman

Inventor： Andy Kahn ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Steven R. Kleiman

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/09 ,  G11C29/00 ,  H03M13/00

CPC classification number: G06F11/1076 ,  G11B20/18 ,  H03M13/096

Abstract: A method and apparatus for a reliable data storage system using block level checksums appended to data blocks. Files are stored on hard disks in storage blocks, including data blocks and block-appended checksums. The block-appended checksum includes a checksum of the data block, a VBN, a DBN, and an embedded checksum for checking the integrity of the block-appended checksum itself. A file system includes file blocks with associated block-appended checksum to the data blocks. The file blocks with block-appended checksums are written to storage blocks. In a preferred embodiment a collection of disk drives are formatted with 520 bytes of data per sector. For each 4,096-byte file block, a corresponding 64-byte block-appended checksum is appended to the file block with the first 7 sectors including most of the file block data while the 8th sector includes the remaining file block data and the 64-byte block-appended checksum.

Abstract translation: 一种使用附加到数据块的块级校验和的可靠数据存储系统的方法和装置。 文件存储在存储块中的硬盘上，包括数据块和块附加校验和。 块附加的校验和包括数据块的校验和，VBN，DBN和用于检查块附加校验和本身的完整性的嵌入校验和。 文件系统包括具有与数据块相关联的块附加校验和的文件块。 具有块附加校验和的文件块被写入存储块。 在优选实施例中，磁盘驱动器的集合被格式化为每扇区520字节的数据。 对于每个4,096字节的文件块，相应的64字节的块附加校验和被附加到文件块，前7个扇区包括大部分文件块数据，而第8个扇区包括剩余的 文件块数据和64字节的块附加校验和。

公开(公告)号：US06944065B2

公开(公告)日：2005-09-13

申请号：US10877634

申请日：2004-06-25

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US20050080947A1

公开(公告)日：2005-04-14

申请号：US10971031

申请日：2004-10-25

Applicant: Joseph Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

Inventor： Joseph Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

IPC: G06F13/00 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40058 ,  H04L12/40065 ,  H04L47/13 ,  H04L49/205

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits using the allocated isochronous channel. In a third variation, multiple receiving nodes that need to receive streaming data from a single transmitting node share a common isochronous data channel. In any of these variations, each receiver can periodically transmit a “deadman” timer message on a broadcast channel to indicate that it is still receiving on a given channel. If a transmitter detects that the deadman timer has expired, it reverts to transmitting data using a “best-efforts” scheme. A transmitter can transmit both to receivers that can handle QoS services and those that cannot explicitly support QoS services.

Abstract translation: 本发明通过具有同步数据传输能力的计算机总线提供服务质量（QoS）传递服务。 总线上的发送节点向指定的接收者发送指示所请求的连接带宽的消息。 如果预期的接收者有足够的资源，它将在总线上分配一个同步数据信道，并向发射机通知所分配的信道。 此后，发射机在分配的信道上发送数据。 如果接收者不能分配信道，则它不响应，并且发射机此后检测到超时条件，并且使用“尽力而为”的方案开始发送（即，非保证的时间传递）。 在第二变体中，接收节点检测到它正在从发送节点接收大量的数据。 作为响应，接收节点在总线上分配等时数据信道，并向发射机通知所分配的信道。 此后，发射机使用所分配的同步信道进行发射。 在第三变型中，需要从单个发射节点接收流数据的多个接收节点共享公共同步数据信道。 在这些变型中的任何一个中，每个接收机可以在广播信道上周期性地发送“死机”定时器消息，以指示它仍然在给定信道上接收。 如果发射机检测到死机定时器已经过期，则它将恢复为使用“尽力而为”方案发送数据。 发射机可以将两者传输到可以处理QoS服务的接收机和不能明确支持QoS服务的接收机。

公开(公告)号：US06799284B1

公开(公告)日：2004-09-28

申请号：US09797007

申请日：2001-02-28

Applicant: Kayuri Patel ,  Raymond Chen ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Andy Kahn

Inventor： Kayuri Patel ,  Raymond Chen ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Andy Kahn

IPC: G06F1100

CPC classification number: G06F11/1076

Abstract: The invention provides a method and system for reducing RAID parity computation following a RAID subsystem failure. Ranges of RAID stripes are assigned to bits in a bitmap that is stored on disk. When writes to the RAID are in progress, the bit associated with the range of stripes in the bitmap is set. When a failure occurs during the write process, the bitmap is analyzed on reboot to determine which ranges of stripes where in the process of being written, and the parity data for only those ranges of stripes is recomputed. Efficiency is increased by use of an in-memory write counter that tracks multiple writes to each stripe range. Using the write counter, the bitmap is written to disk only after each cycle of its associated bitmap bit being set to a value of 1 and then returning to zero. The invention may be installed, modified, and removed at will from a RAID array, and this may be accomplished while the system is in operation.

Abstract translation: 本发明提供了一种用于在RAID子系统故障之后减少RAID奇偶校验计算的方法和系统。 RAID条带的范围分配给存储在磁盘上的位图中的位。 当对RAID的写入进行中，与位图中的条带范围相关联的位被设置。 当在写入过程中发生故障时，在重新启动时分析位图，以确定在写入过程中哪个条带范围，并且仅重新计算那些条带范围的奇偶校验数据。 通过使用跟踪对每个条带范围的多次写入的内存中写计数器来提高效率。 使用写计数器，位图仅在其相关位图位的每个周期设置为1，然后返回到零后才写入磁盘。 本发明可以随意地从RAID阵列安装，修改和移除，并且这可以在系统运行时完成。

公开(公告)号：US06629047B1

公开(公告)日：2003-09-30

申请号：US09539475

申请日：2000-03-30

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

IPC: G11C1300

CPC classification number: G11C5/147 ,  G11C16/225

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract translation: 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

公开(公告)号：US06477091B2

公开(公告)日：2002-11-05

申请号：US09823463

申请日：2001-03-30

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US20140317474A1

公开(公告)日：2014-10-23

申请号：US13997246

申请日：2011-12-30

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

公开(公告)号：US20120120722A1

公开(公告)日：2012-05-17

申请号：US12946612

申请日：2010-11-15

Applicant: Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

Inventor： Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

IPC: G11C11/21

CPC classification number: G11C13/0004 ,  G06F2213/0038 ,  G11C7/1039 ,  G11C13/0061 ,  G11C13/0069

Abstract: An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.

Abstract translation: 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。