公开(公告)号：US06944065B2

公开(公告)日：2005-09-13

申请号：US10877634

申请日：2004-06-25

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US06477091B2

公开(公告)日：2002-11-05

申请号：US09823463

申请日：2001-03-30

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US07319616B2

公开(公告)日：2008-01-15

申请号：US10713841

申请日：2003-11-13

Applicant: Rajesh Sundaram ,  Jahanshir Javanifard ,  Kerry D. Tedrow ,  Priya Walimbe ,  Tom H. Ly ,  Raymond W. Zeng

Inventor： Rajesh Sundaram ,  Jahanshir Javanifard ,  Kerry D. Tedrow ,  Priya Walimbe ,  Tom H. Ly ,  Raymond W. Zeng

IPC: G11C16/06

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Abstract translation: 在一个实施例中，本发明包括将负电压提供给存储器阵列的至少一个未选择的字线的方法。 此外，当将负电压提供给未选择的字线时，可以向所选择的字线提供正电压。 在一个实施例中，存储器阵列可以是并入多级单元架构的闪速存储器。

公开(公告)号：US06788584B2

公开(公告)日：2004-09-07

申请号：US10078106

申请日：2002-02-19

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US06359814B1

公开(公告)日：2002-03-19

申请号：US09753351

申请日：2000-12-29

Applicant: Rajesh Sundaram ,  Kerry D. Tedrow

Inventor： Rajesh Sundaram ,  Kerry D. Tedrow

IPC: G11C700

CPC classification number: H02M3/07 ,  G11C11/22 ,  H02M2003/071

Abstract: A negative voltage charge pump including a regulation circuit. The regulation circuit has a level shift ladder including a plurality of level shifters connected in series. One end of the level shift ladder receives a power supply voltage and the other end receives the negative output of the charge pump. A feedback voltage is generated from one of the intermediate nodes of the level shift ladder. A differential amplifier generates a regulation voltage which varies as a function of the feedback voltage and a reference voltage. The regulation voltage is applied to a frequency control input of a voltage-controlled oscillator for generating a signal that drives the charge pump. Each of the level shifters of the level shift ladder can be a triple well device that can be configured to handle negative voltages without forward biasing an internal p-n junction.

Abstract translation: 负电压电荷泵，包括调节电路。 调节电路具有包括串联连接的多个电平移位器的电平移位梯形图。 电平转换梯的一端接收电源电压，另一端接收电荷泵的负输出。 从电平转换梯的中间节点之一产生反馈电压。 差分放大器产生作为反馈电压和参考电压的函数而变化的调节电压。 调节电压被施加到压控振荡器的频率控制输入端，用于产生驱动电荷泵的信号。 电平变换梯级的每个电平移位器可以是三阱器件，其可被配置为处理负电压而不向前偏置内部p-n结。

公开(公告)号：US07139205B1

公开(公告)日：2006-11-21

申请号：US11026510

申请日：2004-12-30

Applicant: Matthew Goldman ,  Kerry D. Tedrow ,  Gerald J. Barkley ,  Alec W. Smidt

Inventor： Matthew Goldman ,  Kerry D. Tedrow ,  Gerald J. Barkley ,  Alec W. Smidt

IPC: G11C7/00

CPC classification number: G11C8/08

Abstract: An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.

Abstract translation: 一种用于对用于访问高速存储器阵列中的存储器单元的高速字线预充电中间节点的装置和方法。 该设备将位于字线电源电压和字线之间的本地电容预充电至大于字线电源电压的电压电平。 一旦选择了字线，存储在本地电容上的电荷可以与字线的电容快速共享。 可以将字线电源电压施加到本地电容以提供小的增量电压以将字线移动到其最终电压，从而提高系统的响应时间。

公开(公告)号：US06697282B1

公开(公告)日：2004-02-24

申请号：US09676583

申请日：2000-09-29

Applicant: Stephen N. Keeney ,  Kerry D. Tedrow ,  Krishna Kumar Parat

Inventor： Stephen N. Keeney ,  Kerry D. Tedrow ,  Krishna Kumar Parat

IPC: G11C1628

CPC classification number: G11C16/28

Abstract: A reference voltage generator for a flash memory is described. Specifically, the memory cells used in implementing a reference voltage generator are increased in size to enable the generator to be less sensitive to temperature changes as well as device noise. The flash cells may be coupled to threshold tuning devices, which enable the threshold voltage to be easily trimmed.

Abstract translation: 描述了用于闪速存储器的参考电压发生器。 具体地说，用于实现参考电压发生器的存储单元的尺寸增加，使得发生器对温度变化以及器件噪声不太敏感。 闪存单元可以耦合到阈值调谐装置，这使得能够容易地修剪阈值电压。

公开(公告)号：US06515906B2

公开(公告)日：2003-02-04

申请号：US09752714

申请日：2000-12-28

Applicant: Kerry D. Tedrow ,  Balaji Srinivasan ,  Owen W. Jungroth

Inventor： Kerry D. Tedrow ,  Balaji Srinivasan ,  Owen W. Jungroth

IPC: G11C1606

CPC classification number: G11C16/28

Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.

公开(公告)号：US06504760B1

公开(公告)日：2003-01-07

申请号：US09888252

申请日：2001-06-22

Applicant: Kerry D. Tedrow

Inventor： Kerry D. Tedrow

IPC: G11C1604

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3454

Abstract: The present invention is in the field of charging a capacitance of a memory cell. Embodiments of the present invention program a memory cell by determining programming pulses to be used to program the memory cell based on a target state and the memory cell's response to previous program pulses.

Abstract translation: 本发明在对存储单元的电容进行充电的领域中。 本发明的实施例通过基于目标状态确定用于编程存储器单元的编程脉冲和存储器单元对先前编程脉冲的响应来对存储器单元进行编程。

公开(公告)号：US5524266A

公开(公告)日：1996-06-04

申请号：US246779

申请日：1994-05-20

Applicant: Kerry D. Tedrow ,  Jahanshir J. Javanifard ,  Cesar Galindo

Inventor： Kerry D. Tedrow ,  Jahanshir J. Javanifard ,  Cesar Galindo

IPC: G11C5/14 ,  H02M3/07 ,  G06F1/06 ,  G06F1/26

CPC classification number: G11C5/145 ,  H02M3/073

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Abstract translation: 包括多级的集成电路电荷泵电路，每级包括具有与所有其它级的源极和漏极端子串联连接的源极和漏极端子的第一N型场效应开关晶体管器件，第二N型场效应控制 具有连接第一开关晶体管器件的漏极端子和栅极端子的漏极和源极端子的晶体管器件和连接到第一器件的源极端子的存储电容器; 要被泵送的电压源连接到第一级的第一器件的漏极端子。 第一系列时钟脉冲被施加到电荷泵的每隔一级的第一开关晶体管器件的栅极端子和第二控制晶体管器件的栅极端子之间; 并且不与第一系列时钟脉冲重叠的第二系列时钟脉冲在电荷泵的交替级中施加到第一开关晶体管器件的栅极端子，并且在第二组控制晶体管器件的栅极端子之间分阶段地施加 替代阶段。 这些脉冲使得开关晶体管以交替的方式导通和截止，使得栅极端子比漏极端子高，使得电荷在级之间没有阈值下降而被传送，并且高电压被泵送到输出端 终奌站。