公开(公告)号：US06902993B2

公开(公告)日：2005-06-07

申请号：US10402750

申请日：2003-03-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

IPC: H01L21/28 ,  H01L21/324 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/4941 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/78

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract translation: 在一个实施例中，通过在硅层上进行第一热处理，在硅层上形成金属堆叠，并在金属堆上进行第二热处理，形成晶体管的栅极。 第一热处理可以是快速热退火步骤，而第二热处理可以是快速热氮化步骤。 所得到的栅极在硅层和金属堆叠之间表现出相对较低的界面接触电阻，因此可有利地用于高速器件中。

公开(公告)号：US06841491B1

公开(公告)日：2005-01-11

申请号：US10039469

申请日：2001-11-08

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar

IPC: H01L21/027 ,  H01L21/318 ,  H01L21/31

CPC classification number: H01L21/0276 ,  H01L21/3185

Abstract: A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

Abstract translation: 一种用于制造半导体结构的工艺包括用第一工具在半导体衬底上沉积氮化物层，并在第一工具上在半导体衬底上沉积抗反射层。 氮化物层包括硅和氮。

公开(公告)号：US06838392B1

公开(公告)日：2005-01-04

申请号：US10119574

申请日：2002-04-09

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/02052 ,  H01L21/31111 ,  H01L21/76232

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

公开(公告)号：US06818558B1

公开(公告)日：2004-11-16

申请号：US10185470

申请日：2002-06-28

Applicant: Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

Inventor： Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

IPC: H01L21311

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7882

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract translation: 公开了形成电荷存储层的方法。 根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分 流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（ 步骤106）。

公开(公告)号：US06774452B1

公开(公告)日：2004-08-10

申请号：US10321965

申请日：2002-12-17

Applicant: Krishnaswamy Ramkumar ,  Sharmin Sadoughi

Inventor： Krishnaswamy Ramkumar ,  Sharmin Sadoughi

IPC: H01L2176

CPC classification number: H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Abstract translation: 公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。 该结构还包括电介质层和金属层。 介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。 电介质层填充隔离沟槽并且不填充对准沟槽。 金属层位于电介质层上。

公开(公告)号：US06680516B1

公开(公告)日：2004-01-20

申请号：US10313267

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L2976

CPC classification number: H01L21/76897 ,  H01L29/42372

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract translation: 半导体结构包括半导体衬底，半导体衬底上的栅极层，栅极层上的金属层以及金属层上的蚀刻停止层。 衬底与蚀刻停止层的顶部之间的距离是栅堆叠高度，栅叠层高度至多为2700埃。 此外，蚀刻停止层的厚度至少为800埃。

公开(公告)号：US09102522B2

公开(公告)日：2015-08-11

申请号：US13434347

申请日：2012-03-29

Applicant: Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

IPC: H01L21/336 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105

CPC classification number: B82Y10/00 ,  H01L21/28282 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

公开(公告)号：US08993453B1

公开(公告)日：2015-03-31

申请号：US13620071

申请日：2012-09-14

Applicant: Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

Abstract translation: 描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。 在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于 第二次暴露的晶面。 然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度 层大致等于电介质层的第二部分的厚度。

公开(公告)号：US08871595B2

公开(公告)日：2014-10-28

申请号：US13436878

申请日：2012-03-31

Applicant: Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

IPC: H01L21/8239

CPC classification number: H01L29/7833 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7836 ,  H01L29/7843 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：US08643124B2

公开(公告)日：2014-02-04

申请号：US13007533

申请日：2011-01-14

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L21/336

CPC classification number: H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。