FMCW chirp bandwidth control
    41.
    发明授权

    公开(公告)号:US11789137B2

    公开(公告)日:2023-10-17

    申请号:US17138549

    申请日:2020-12-30

    Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.

    Frequency synthesizer output cycle counter including ring encoder

    公开(公告)号:US11486916B2

    公开(公告)日:2022-11-01

    申请号:US17515637

    申请日:2021-11-01

    Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

    Methods and apparatus for velocity detection in MIMO radar including velocity ambiguity resolution

    公开(公告)号:US11378649B2

    公开(公告)日:2022-07-05

    申请号:US16814531

    申请日:2020-03-10

    Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

    Loopback techniques for synchronization of oscillator signal in radar

    公开(公告)号:US11035928B2

    公开(公告)日:2021-06-15

    申请号:US15642880

    申请日:2017-07-06

    Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

    NOISE MITIGATION IN RADAR SYSTEMS
    46.
    发明申请

    公开(公告)号:US20210011118A1

    公开(公告)日:2021-01-14

    申请号:US17020931

    申请日:2020-09-15

    Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.

    Methods and Apparatus for Velocity Detection in MIMO Radar Including Velocity Ambiguity Resolution

    公开(公告)号:US20200209352A1

    公开(公告)日:2020-07-02

    申请号:US16814531

    申请日:2020-03-10

    Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

    Frequency synthesizer output cycle counter including ring encoder

    公开(公告)号:US10481187B2

    公开(公告)日:2019-11-19

    申请号:US14588014

    申请日:2014-12-31

    Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

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