公开(公告)号：US20150279729A1

公开(公告)日：2015-10-01

申请号：US14229264

申请日：2014-03-28

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Geng-Shuoh Chang ,  Chun-Sheng Wu ,  Chun-Li Lin ,  Yi-Fang Li ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer formed over the semiconductor substrate, a first anti-etch layer, a second anti-etch layer and a conductive material. The dielectric layer has an opening. The first anti-etch layer is formed on the sidewall of the opening and made of a material having resistance to peroxide. The second anti-etch layer is formed over the first anti-etch layer and made of a material having resistance to acid. The conductive material is formed within the opening and in contact with the second anti-etch layer.

Abstract translation: 半导体结构包括半导体衬底，形成在半导体衬底上的电介质层，第一抗蚀刻层，第二抗蚀刻层和导电材料。 电介质层具有开口。 第一抗蚀刻层形成在开口的侧壁上并由具有过氧化物的材料制成。 第二抗蚀刻层形成在第一抗蚀刻层上并由耐酸性的材料制成。 导电材料形成在开口内并与第二抗蚀刻层接触。

公开(公告)号：US20140349471A1

公开(公告)日：2014-11-27

申请号：US14456082

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Chiang ,  Kuang-Cheng Wu ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/66545

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及集成电路（IC）。 IC包括具有上表面的半导体衬底，源表面和漏区附近。 在源极区域和漏极区域之间的衬底中设置沟道区域。 栅电极设置在沟道区上方并通过栅极电介质与沟道区分离。 侧壁间隔件围绕栅电极的相对侧壁形成。 侧壁间隔件的上外边缘向外延伸超过侧壁间隔件的相应的下外边缘。 衬套设置在侧壁间隔物的相对侧壁周围，并且在衬垫的上部具有第一厚度，在衬垫的下部具有第二厚度。 第一厚度小于第二厚度。 还公开了其他实施例。

公开(公告)号：US20140231671A1

公开(公告)日：2014-08-21

申请号：US13771112

申请日：2013-02-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ying LU ,  Sung-Po Yang ,  Ding-I Liu ,  Kuo-Shu Tseng ,  Chung-Wen Chang

IPC: B05D3/06

CPC classification number: B05D3/067 ,  H01L21/67115 ,  H01L21/6776

Abstract: A UV curing system includes an enclosure defining an interior, a UV radiation source disposed within the interior of the enclosure, and a first window disposed within the interior of the enclosure. The first window creates a barrier that separates the UV radiation source and a processing chamber. A second window is disposed within the interior of the enclosure at a distance from the first window to define a gas channel. The second window defines a plurality of openings such that the gas channel is in fluid communication with the processing chamber. A gas inlet conduit is in fluid communication with the gas channel and is configured to introduce a cooling gas into the gas channel. A gas outlet is in fluid communication with the processing chamber and is configured to remove gas from the processing chamber.

Abstract translation: UV固化系统包括限定内部的外壳，设置在外壳内部的UV辐射源以及设置在外壳内部的第一窗口。 第一个窗口创建一个隔离UV辐射源和一个处理室的屏障。 第二窗口设置在与第一窗口相距一定距离的外壳的内部，以限定气体通道。 第二窗口限定多个开口，使得气体通道与处理室流体连通。 气体入口导管与气体通道流体连通，并且构造成将冷却气体引入气体通道。 气体出口与处理室流体连通并且被配置为从处理室去除气体。

公开(公告)号：US20140120706A1

公开(公告)日：2014-05-01

申请号：US13660363

申请日：2012-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： LI Chen ,  Jyh-Nan Lin ,  Chin-Feng Sun ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/283

CPC classification number: H01L21/283 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76801

Abstract: A method of forming an interlayer dielectric film above a metal gate of a metal oxide semiconductor device comprises forming a metal gate above a semiconductor substrate; and forming the interlayer dielectric film above the metal gate by reacting a silicon-containing compound as precursor and a reactant for oxidizing the silicon-containing compound. The silicon-containing compound has the formula: Six(A)y(B)z(C)m(D)n   (I) wherein x is in the range of from 1 to 9; y+z+m+n is in the range of from 4 to 20; and A, B, C, and D independently represent a functional group connecting with a silicon atom. The functional group is selected from a group consisting of alkyl, alkenyl, alkynyl, aryl, alkylaryl, alkoxyl, alkylcarbonyl, carboxyl, alkylcarbonyloxy, amide, amino, alkylcarbonylamino, —NO2, and —CN.

Abstract translation: 在金属氧化物半导体器件的金属栅极上形成层间电介质膜的方法包括在半导体衬底上形成金属栅极; 以及通过使含硅化合物作为前体和用于氧化含硅化合物的反应物反应，在金属栅上方形成层间电介质膜。 含硅化合物具有下式：其中x在1至9的范围内的六（A）y（B）z（C）m（D）n（I） y + z + m + n在4至20的范围内; A，B，C和D独立地表示与硅原子连接的官能团。 官能团选自烷基，烯基，炔基，芳基，烷基芳基，烷氧基，烷基羰基，羧基，烷基羰基氧基，酰胺，氨基，烷基羰基氨基，-NO 2和-CN。