公开(公告)号：US11043567B2

公开(公告)日：2021-06-22

申请号：US16115390

申请日：2018-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/165 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.

公开(公告)号：US11038059B2

公开(公告)日：2021-06-15

申请号：US16515020

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Sheng Liang ,  Kuo-Hua Pan ,  Hsin-Che Chiang ,  Ming-Heng Tsai

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US20200335337A1

公开(公告)日：2020-10-22

申请号：US16916116

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/033 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764

Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.

公开(公告)号：US10714342B2

公开(公告)日：2020-07-14

申请号：US16164779

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/033 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764

Abstract: Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US20200044074A1

公开(公告)日：2020-02-06

申请号：US16515020

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Sheng Liang ,  Kuo-Hua Pan ,  Hsin-Che Chiang ,  Ming-Heng Tsai

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US10529629B2

公开(公告)日：2020-01-07

申请号：US15966299

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US10134873B2

公开(公告)日：2018-11-20

申请号：US15355901

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51

Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.

公开(公告)号：US12170320B2

公开(公告)日：2024-12-17

申请号：US18309564

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chia Tai ,  Ju-Yuan Tzeng ,  Hsin-Che Chiang ,  Yuan-Sheng Huang ,  Chun-Sheng Liang

IPC: H01L29/417 ,  H01L21/3065 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

公开(公告)号：US11837602B2

公开(公告)日：2023-12-05

申请号：US17328016

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-San Chien ,  Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/0245 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

公开(公告)号：US11670695B2

公开(公告)日：2023-06-06

申请号：US17232644

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chia Tai ,  Ju-Yuan Tzeng ,  Hsin-Che Chiang ,  Yuan-Sheng Huang ,  Chun-Sheng Liang

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/3065 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.