公开(公告)号：US20240249976A1

公开(公告)日：2024-07-25

申请号：US18603483

申请日：2024-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Jeng-Ya David Yeh ,  Chung-Sheng Liang ,  Ju-Li Huang

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417

CPC分类号： H01L21/7682 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

摘要： In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US20220173226A1

公开(公告)日：2022-06-02

申请号：US17676335

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10529629B2

公开(公告)日：2020-01-07

申请号：US15966299

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US11295990B2

公开(公告)日：2022-04-05

申请号：US16735184

申请日：2020-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US11031500B2

公开(公告)日：2021-06-08

申请号：US16287368

申请日：2019-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang ,  Chun-Ming Yang ,  Yu-Chi Pan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

摘要： The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US10755970B2

公开(公告)日：2020-08-25

申请号：US16009519

申请日：2018-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC分类号： H01L29/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

摘要： In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US10283417B1

公开(公告)日：2019-05-07

申请号：US15833721

申请日：2017-12-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

摘要： Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further includes a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer includes metal phosphate and the second self-protective layer includes boron including complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.

公开(公告)号：US20240203740A1

公开(公告)日：2024-06-20

申请号：US18427512

申请日：2024-01-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28247 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66795 ,  H01L21/28079

摘要： Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US11923201B2

公开(公告)日：2024-03-05

申请号：US17187176

申请日：2021-02-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28247 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66795 ,  H01L21/28079

摘要： Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US11257924B2

公开(公告)日：2022-02-22

申请号：US16746097

申请日：2020-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.