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    MRAM memory cell layout for minimizing bitcell area
    42.
    发明授权
    MRAM memory cell layout for minimizing bitcell area 有权

    公开(公告)号：US11244983B2

    公开(公告)日：2022-02-08

    申请号：US16893010

    申请日：2020-06-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.

    METHOD FOR MRAM TOP ELECTRODE CONNECTION
    43.
    发明申请
    METHOD FOR MRAM TOP ELECTRODE CONNECTION 有权

    公开(公告)号：US20210375987A1

    公开(公告)日：2021-12-02

    申请号：US16884353

    申请日：2020-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen ,  Sheng-Huang Huang

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.

    SIDEWALL SPACER STRUCTURE FOR MEMORY CELL
    45.
    发明申请
    SIDEWALL SPACER STRUCTURE FOR MEMORY CELL 有权

    公开(公告)号：US20210111333A1

    公开(公告)日：2021-04-15

    申请号：US16601723

    申请日：2019-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Wen Chang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Sheng-Huang Huang ,  Chia-Hua Lin

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

    Techniques for MRAM MTJ top electrode to metal layer interface including spacer
    49.
    发明授权
    Techniques for MRAM MTJ top electrode to metal layer interface including spacer 有权

    公开(公告)号：US10522740B2

    公开(公告)日：2019-12-31

    申请号：US15991004

    申请日：2018-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

    IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in contact with the upper metal layer. A sidewall spacer surrounds an outer periphery of the top electrode. An etch stop layer is disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer. The etch stop layer overhangs the outer periphery of the spacer top surface.

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