公开(公告)号：US11574857B2

公开(公告)日：2023-02-07

申请号：US16827595

申请日：2020-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Chien-Chang Lin

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/16 ,  H01L21/48 ,  H01L25/18

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

公开(公告)号：US11569562B2

公开(公告)日：2023-01-31

申请号：US16997958

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ping Wang ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Chung-Yi Hsu

IPC: H01Q1/22 ,  H01Q9/04 ,  H01L23/31 ,  H01L23/66

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

公开(公告)号：US20220320024A1

公开(公告)日：2022-10-06

申请号：US17844876

申请日：2022-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Hsiang Chuang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Kai-Chiang Wu ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

公开(公告)号：US11282779B2

公开(公告)日：2022-03-22

申请号：US16796905

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Jiun-Yi Wu ,  Yu-Min Liang

IPC: H01L23/498 ,  H01L23/00

Abstract: A package structure including a first circuit board structure, a redistribution layer structure, bonding elements, and a semiconductor package is provided. The redistribution layer structure is disposed over and electrically connected to the first circuit board structure. The bonding elements are disposed between and electrically connected to the redistribution layer structure and the first circuit board structure. Each of the bonding elements has a core portion and a shell portion surrounding the core portion. A stiffness of the core portion is higher than a stiffness of the shell portion. A semiconductor package is disposed over and electrically connected to the redistribution layer structure.

公开(公告)号：US20220028773A1

公开(公告)日：2022-01-27

申请号：US16934024

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Jiun-Yi Wu ,  Kai-Chiang Wu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/683

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.

公开(公告)号：US11145595B2

公开(公告)日：2021-10-12

申请号：US16706805

申请日：2019-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US11018083B2

公开(公告)日：2021-05-25

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20200343203A1

公开(公告)日：2020-10-29

申请号：US16924116

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US20200035625A1

公开(公告)日：2020-01-30

申请号：US16421497

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48

Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.

公开(公告)号：US20200020640A1

公开(公告)日：2020-01-16

申请号：US16578403

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.