公开(公告)号：US11018083B2

公开(公告)日：2021-05-25

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20200091097A1

公开(公告)日：2020-03-19

申请号：US16133705

申请日：2018-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Hung-Jui Kuo ,  Hsin-Yu Pan ,  Ming-che Ho ,  Tzu Yun Huang ,  Yen-Fu Su

IPC: H01L23/00

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

公开(公告)号：US20230223357A1

公开(公告)日：2023-07-13

申请号：US17752272

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Chien-Hsun Chen ,  Tuan-Yu Hung ,  Hsin-Yu Pan ,  Wei-Kang Hsieh ,  Tsung-Hsien Chiang ,  Chao-Hsien Huang ,  Tzu-Sung Huang ,  Ming Hung Tseng ,  Wei-Chih Chen ,  Ban-Li Wu ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/214 ,  H01L2221/68359 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

公开(公告)号：US11004812B2

公开(公告)日：2021-05-11

申请号：US16133705

申请日：2018-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Hung-Jui Kuo ,  Hsin-Yu Pan ,  Ming-che Ho ,  Tzu Yun Huang ,  Yen-Fu Su

IPC: H01L23/00

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

公开(公告)号：US20210020559A1

公开(公告)日：2021-01-21

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01L21/768 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.