公开(公告)号：US10212254B1

公开(公告)日：2019-02-19

申请号：US15217579

申请日：2016-07-22

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： H04L29/08 ,  G06F9/50 ,  H04L29/06

摘要： A mechanism that enables multiple Mobile Devices to operate in clusters is provided. Using the mobile cluster mechanism framework provided in this invention, Mobile Devices can execute compute intensive tasks in the field by sharing the task between various devices. The invention also contemplates various options of implementing the cluster mechanism on Mobile Devices. The invention further contemplates solutions for the roaming of Mobile Devices.

公开(公告)号：US08458453B1

公开(公告)日：2013-06-04

申请号：US12356220

申请日：2009-01-20

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： H04L29/06

CPC分类号： H04L12/462 ,  H04L29/12028 ,  H04L61/103 ,  H04L61/2015 ,  H04L63/0272 ,  H04L63/0428

摘要： A system and method of providing secure communications between two or more hosts connected to a public network, where a secure virtual network (SVN) is established among the two or more hosts.

摘要翻译： 一种在连接到公共网络的两个或多个主机之间提供安全通信的系统和方法，其中在两个或更多个主机之间建立安全虚拟网络（SVN）。

公开(公告)号：US06912196B1

公开(公告)日：2005-06-28

申请号：US09571027

申请日：2000-05-15

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： H04L12/437 ,  H04L12/26

CPC分类号： H04L12/437

摘要： A packet architecture, communication system, and method are provided for determining the location at which a network is disrupted, disabled, and/or severed. The packet can contain control bits and error identification bits which note the location at which disturbance exists, and informs the originating module to take alternative path if necessary. The alternative path can be applied to either re-sending the existing packet or sending future packets between certain modules connected to the network, wherein the network preferably includes one or more ring topologies interconnected with one another between termination devices. The termination devices allow communication across subnets which form an intranet or across a global system, or internet. Although redundant transmission channels are used, each transmission channel preferably does not send redundant packets, nor are the transmission channels dedicated as uni-directional. Instead, each of the redundant transmission channels can send dissimilar packets in a bi-directional fashion.

摘要翻译： 提供分组架构，通信系统和方法，用于确定网络中断，禁用和/或断开的位置。 分组可以包含控制位和错误识别位，其记录干扰存在的位置，并且如果需要，通知始发模块采取替代路径。 替代路径可以应用于重新发送现有分组或在连接到网络的某些模块之间发送未来分组，其中网络优选地包括在终端设备之间彼此互连的一个或多个环形拓扑。 终端设备允许在形成内部网或跨全球系统或互联网的子网之间进行通信。 虽然使用冗余传输信道，但是每个传输信道优选地不发送冗余分组，传输信道也不是专用的单向的。 相反，每个冗余传输信道可以以双向方式发送不相似的分组。

公开(公告)号：US06788701B1

公开(公告)日：2004-09-07

申请号：US09312240

申请日：1999-05-14

申请人： Rupaka Mahalingaiah ,  Viren H. Kapadia

发明人： Rupaka Mahalingaiah ,  Viren H. Kapadia

IPC分类号： H04L1254

CPC分类号： H04L45/04

摘要： An architecture, system and method are provided for efficiently transferring packets of data across a communication network. The communication network is structured such that there are hierarchical levels of high speed switches existing throughout the network. Distributed routing of packets is achieved by comparing identification numbers of only select switches with the destination address on a field-by-field basis. Not all fields need be compared at all switches. Once routing is achieved within the structured network, transfer to a destination termination device occurs through a single look-up table only when departing the network if multiple termination devices are present at that exit node. The routing operation between termination devices can therefore be achieved using a single mapping operation (if more than one termination device must be selected) and is backward compatible with devices external to the network and protocols used by those devices. An additional protocol layer specific to the structure is wrapped onto the incoming packet protocol using a series of read cycles to a memory which temporarily receives the incoming protocol. The sequence of reads can be quickly achieved without using conventional packet processors and the delayed access times normally attributed to those processors. Each switch thereby serves as a traffic manager, having registers that are configured so as to allow the traffic manager to direct packets of data from an input port to an output port in the quickest, most efficient manner without having to decode the entire destination address or requiring time-consumptive routing tables.

摘要翻译： 提供了一种用于通过通信网络有效地传送数据分组的架构，系统和方法。 通信网络被构造成使得在整个网络中存在分层级的高速交换机。 分组的分布式路由是通过逐个场地比较仅选择交换机的标识号与目的地地址来实现的。 并不是所有的开关都需要比较。 一旦在结构化网络内实现了路由，只有当离开网络时，如果在该出口节点处存在多个终端设备，则通过单个查找表传送到目的地终端设备。 因此，可以使用单一映射操作（如果必须选择多个终端设备）并且向后兼容网络外部设备和这些设备使用的协议，则可以实现终端设备之间的路由操作。 特定于该结构的附加协议层使用一系列对临时接收传入协议的存储器的读周期来包装到传入分组协议上。 无需使用传统的分组处理器和通常归因于这些处理器的延迟访问时间，可以快速实现读取顺序。 因此，每个交换机用作流量管理器，其具有被配置为允许流量管理器以最快，最有效的方式将数据从输入端口引导到输出端口的寄存器，而不必解码整个目的地地址或 需要耗时的路由表。

公开(公告)号：US06360317B1

公开(公告)日：2002-03-19

申请号：US09702220

申请日：2000-10-30

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F932

CPC分类号： G06F9/382 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3853 ,  G06F9/3857

摘要： A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit. The floating point instruction unit receives the exchange register information, exchanges the top-of-stack with the register specified by the exchange register information and then performs the floating point operation. In the above manner, two floating point operations may be executed in a single clock cycle.

摘要翻译： 微处理器检测浮点交换指令后跟浮点指令，并将两条指令作为一个组合指令分派到浮点单元。 预解码单元将两个指令标记为单个指令。 对于浮点交换指令的第一个字节，一个起始位被置位，而对于浮点指令的最后一个字节，一个结束位被置位。 组合指令被分派到指令执行管道中。 解码单元解码两个指令的操作码，并将浮点指令的操作码传递到浮点单元，并将交换寄存器信息传递给浮点单元。 交换寄存器信息包括足够数量的位以指定浮点寄存器和有效位。 浮点指令单元接收交换寄存器信息，与由交换寄存器信息指定的寄存器交换栈顶，然后执行浮点运算。 以上述方式，可以在单个时钟周期中执行两个浮点运算。

公开(公告)号：US6167507A

公开(公告)日：2000-12-26

申请号：US261886

申请日：1999-03-03

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3853 ,  G06F9/3857

摘要： A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit. The floating point instruction unit receives the exchange register information, exchanges the top-of-stack with the register specified by the exchange register information and then performs the floating point operation. In the above manner, two floating point operations may be executed in a single clock cycle.

摘要翻译： 微处理器检测浮点交换指令后跟浮点指令，并将两条指令作为一个组合指令分派到浮点单元。 预解码单元将两个指令标记为单个指令。 对于浮点交换指令的第一个字节，一个起始位被置位，而对于浮点指令的最后一个字节，一个结束位被置位。 组合指令被分派到指令执行管道中。 解码单元解码两个指令的操作码，并将浮点指令的操作码传递到浮点单元，并将交换寄存器信息传递给浮点单元。交换寄存器信息包括足够数量的位来指定浮点寄存器 和一个有效位。 浮点指令单元接收交换寄存器信息，与由交换寄存器信息指定的寄存器交换栈顶，然后进行浮点运算。 以上述方式，可以在单个时钟周期中执行两个浮点运算。

公开(公告)号：US6134670A

公开(公告)日：2000-10-17

申请号：US17418

申请日：1998-02-02

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： G06F1/10 ,  G06F1/12

CPC分类号： G06F1/10

摘要： A distributed clocking mechanism is provided for synchronous digital designs. Each functional unit in the design is associated with a distributed clock unit that generates controlled local clocks. The clock period and the pulse width of local clock can be varied. Multiple clocks with varying phases are generated. The local clocks are synchronized with other local clocks and also with external clock. This controlled, distributed clocking mechanism provides flexibility to the design, increases performance, and reduces power consumption and noise of the device in comparison to traditional synchronous central clocking mechanism. This mechanism also enables the design to operate with multiple external clocks allowing for easy integration of multiple functionality to the design.

摘要翻译： 为同步数字设计提供分布式时钟机制。 设计中的每个功能单元与生成受控本地时钟的分布式时钟单元相关联。 时钟周期和本地时钟的脉冲宽度可以变化。 产生具有不同相位的多个时钟。 本地时钟与其他本地时钟同步，并与外部时钟同步。 与传统的同步中心计时机制相比，这种受控的分布式时钟机制提供了设计的灵活性，增加了性能，降低了设备的功耗和噪声。 该机制还使设计能够与多个外部时钟一起工作，从而可以轻松地将多种功能集成到设计中。

公开(公告)号：US6014741A

公开(公告)日：2000-01-11

申请号：US233312

申请日：1999-01-19

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/34

CPC分类号： G06F9/381 ,  G06F9/3017 ,  G06F9/325

摘要： A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number of iterations of the loop. The microcode sequence that implements the loop includes a microcode instruction that uses the string count as an operand and/or a result. The microcode instruction unit captures the string count when it is available on either an operand or address bus. The string count is compared to the number of iterations of the string loop to determine when to terminate the microcode loop. If the string count is not captured prior to the microcode instruction unit dispatching more microcode instructions than necessary, the microcode instruction unit notifies other components via a cancel bus. In this manner, the end of a loop is detected prior to the functional unit detecting a mispredicted branch instruction within the microcode loop.

摘要翻译： 超标量微处理器实现微代码指令单元，其预测微代码循环的结束。 微代码指令单元检测微代码循环并开始计数循环的迭代次数。 实现循环的微代码序列包括使用字符串计数作为操作数和/或结果的微代码指令。 微码指令单元在操作数或地址总线可用时捕获字符串计数。 将字符串计数与字符串循环的迭代次数进行比较，以确定何时终止微代码循环。 如果在微代码指令单元不需要调度更多微代码指令之前没有捕获字符串计数，则微代码指令单元经由取消总线通知其他组件。 以这种方式，在功能单元检测到微代码循环内的错误预测的分支指令之前检测循环的结束。

公开(公告)号：US06009513A

公开(公告)日：1999-12-28

申请号：US261116

申请日：1999-03-03

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/28 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence. If the last microcode line of the microcode sequence contains less instructions than the number of issue positions available, fastpath, or directly decodable instructions, can be issued with the final microcode line.

公开(公告)号：US5913047A

公开(公告)日：1999-06-15

申请号：US960189

申请日：1997-10-29

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3853 ,  G06F9/3857

摘要： A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit. The floating point instruction unit receives the exchange register information, exchanges the top-of-stack with the register specified by the exchange register information and then performs the floating point operation. In the above manner, two floating point operations may be executed in a single clock cycle.

摘要翻译： 微处理器检测浮点交换指令后跟浮点指令，并将两条指令作为一个组合指令分派到浮点单元。 预解码单元将两个指令标记为单个指令。 对于浮点交换指令的第一个字节，一个起始位被置位，而对于浮点指令的最后一个字节，一个结束位被置位。 组合指令被分派到指令执行管道中。 解码单元解码两个指令的操作码，并将浮点指令的操作码传递到浮点单元，并将交换寄存器信息传递给浮点单元。 交换寄存器信息包括足够数量的位以指定浮点寄存器和有效位。 浮点指令单元接收交换寄存器信息，与由交换寄存器信息指定的寄存器交换栈顶，然后执行浮点运算。 以上述方式，可以在单个时钟周期中执行两个浮点运算。