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139 条记录 (耗时 0.031 秒)

    Multiple-gate MOS transistors
    41.
    发明授权
    Multiple-gate MOS transistors 有权
    多门MOS晶体管

    公开(公告)号：US07755144B2

    公开(公告)日：2010-07-13

    申请号：US12269783

    申请日：2008-11-12

    申请人： Hong-Jyh Li ,  Thomas Schulz

    发明人： Hong-Jyh Li ,  Thomas Schulz

    IPC分类号： H01L27/088 ,  H01L27/092

    CPC分类号： H01L21/823857 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645

    摘要： Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

    摘要翻译： 公开了具有不同栅介电材料的晶体管的半导体器件及其制造方法。 一个实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一晶体管设置在工件的第一区域中，第一晶体管具有至少两个第一栅电极。 第一栅极电介质设置在所述至少两个第一栅电极中的每一个附近，所述第一栅极电介质包括第一材料。 第二晶体管设置在工件的第二区域中，第二晶体管具有至少两个第二栅电极。 第二栅极电介质设置在所述至少两个第二栅电极中的每一个附近，所述第二栅极电介质包括第二材料。 第二种材料与第一种材料不同。

    SRAM device
    42.
    发明授权
    SRAM device 有权
    SRAM器件

    公开(公告)号：US07700999B2

    公开(公告)日：2010-04-20

    申请号：US11773510

    申请日：2007-07-05

    申请人： Thomas Schulz

    发明人： Thomas Schulz

    IPC分类号： H01L23/62

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.

    摘要翻译： 集成电路器件具有限定纵轴的基区。 在示例性实施例中是NMOS晶体管的四个在线晶体管每个以纵轴为中心。 在示例性实施例中，PMOS晶体管的两个偏置晶体管分别偏离纵轴的第一和第二侧。

    MuGFET with increased thermal mass
    43.
    发明授权
    MuGFET with increased thermal mass 有权
    MuGFET具有增加的热质量

    公开(公告)号：US07678632B2

    公开(公告)日：2010-03-16

    申请号：US11561170

    申请日：2006-11-17

    申请人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

    发明人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L23/367 ,  H01L27/0248 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed.

    摘要翻译： 本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态 靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。 还公开了其他实施例。

    SRAM DEVICE
    45.
    发明申请
    SRAM DEVICE 有权
    SRAM设备

    公开(公告)号：US20090008707A1

    公开(公告)日：2009-01-08

    申请号：US11773510

    申请日：2007-07-05

    申请人： Thomas Schulz

    发明人： Thomas Schulz

    IPC分类号： H01L27/11 ,  H01L29/732

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.

    摘要翻译： 集成电路器件具有限定纵轴的基区。 在示例性实施例中是NMOS晶体管的四个在线晶体管每个以纵轴为中心。 在示例性实施例中，PMOS晶体管的两个偏置晶体管分别偏离纵轴的第一和第二侧。

    Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
    46.
    发明授权
    Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials 有权
    制造具有不同栅极电介质材料的多栅极CMOS晶体管的方法

    公开(公告)号：US07462538B2

    公开(公告)日：2008-12-09

    申请号：US11273747

    申请日：2005-11-15

    申请人： Hong-Jyh Li ,  Thomas Schulz

    发明人： Hong-Jyh Li ,  Thomas Schulz

    IPC分类号： H01L21/336 ,  H01L29/80

    CPC分类号： H01L21/823857 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645

    摘要： Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

    摘要翻译： 公开了具有不同栅介电材料的晶体管的半导体器件及其制造方法。 一个实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一晶体管设置在工件的第一区域中，第一晶体管具有至少两个第一栅电极。 第一栅极电介质设置在所述至少两个第一栅电极中的每一个附近，所述第一栅极电介质包括第一材料。 第二晶体管设置在工件的第二区域中，第二晶体管具有至少两个第二栅电极。 第二栅极电介质设置在所述至少两个第二栅电极中的每一个附近，所述第二栅极电介质包括第二材料。 第二种材料与第一种材料不同。

    FIELD EFFECT TRANSISTOR WITH A FIN STRUCTURE
    47.
    发明申请
    FIELD EFFECT TRANSISTOR WITH A FIN STRUCTURE 有权
    具有结构的场效应晶体管

    公开(公告)号：US20080111163A1

    公开(公告)日：2008-05-15

    申请号：US11559656

    申请日：2006-11-14

    申请人： Christian Russ ,  Harald Gossner ,  Thomas Schulz

    发明人： Christian Russ ,  Harald Gossner ,  Thomas Schulz

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/812 ,  H01L21/338 ,  H01L21/44

    CPC分类号： H01L29/785 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78621

    摘要： A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.

    摘要翻译： 一种具有鳍结构的场效应晶体管，具有第一和第二源极/漏极区域; 形成在所述鳍结构内并且在所述第一和第二源极/漏极区之间的体区; 形成在所述第一源极/漏极区域的一部分内的金属导电区域，所述金属导电区域邻近所述体区域或者设置在所述体区域和所述第一源极/漏极区域之间的轻掺杂区域; 以及形成在第二源极/漏极区域的一部分内的电流镇流区域。

    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method
    49.
    发明授权
    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
    具有电容器并具有平面晶体管和制造方法的集成电路装置

    公开(公告)号：US07173302B2

    公开(公告)日：2007-02-06

    申请号：US10531493

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

    摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

    摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。