IMAGE SENSOR AND CONTROL METHOD OF THE IMAGE SENSOR
    41.
    发明申请
    IMAGE SENSOR AND CONTROL METHOD OF THE IMAGE SENSOR 审中-公开
    图像传感器和图像传感器的控制方法

    公开(公告)号:US20100073542A1

    公开(公告)日:2010-03-25

    申请号:US12627780

    申请日:2009-11-30

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: H04N5/335

    CPC分类号: H04N5/37455

    摘要: An image sensor has plural array blocks B1 to B20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.

    摘要翻译: 图像传感器具有以二维(2D)布置排列的多个阵列块B1至B20。 每个阵列块具有子阵列和相应的模数(A / D)转换器,用于执行从子阵列输出的光信号(或检测信号)的A / D转换。 子阵列具有以2D排列布置的多个像素单元。 每个A / D转换器具有串联连接的多级延迟单元的脉冲延迟电路。 每个延迟单元将输入脉冲延迟与从子阵列接收的光信号的电平相对应的延迟时间。 使用脉冲延迟型A / D转换器作为A / D转换器,其输出延迟单元的数量作为输入脉冲经过测量时间段的A / D转换数据项。

    Time measuring circuit with pulse delay circuit
    42.
    发明授权
    Time measuring circuit with pulse delay circuit 有权
    具有脉冲延迟电路的时间测量电路

    公开(公告)号:US07525878B2

    公开(公告)日:2009-04-28

    申请号:US11807712

    申请日:2007-05-30

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: G04F10/00 H03H11/01

    CPC分类号: G04F10/00

    摘要: In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.

    摘要翻译: 在时间测量电路中,脉冲延迟电路具有多个延迟单元。 脉冲延迟电路被配置为在脉冲信号被多个延迟单元延迟的同时通过多个延迟单元传送脉冲信号。 多个延迟单元中的每一个的延迟时间取决于输入到多个延迟单元中的每一个的第一驱动电压的电平。 发电电路被配置为获得脉冲信号在预定时间段内通过的多个延迟单元,作为时间测量数据生成基于获得的数量的数字数据。 第一设置单元被配置为可变地设置输入到多个延迟单元中的每一个的第一驱动电压的电平。

    Analog-to-digital converter with pulse delay circuit
    43.
    发明申请
    Analog-to-digital converter with pulse delay circuit 有权
    具有脉冲延迟电路的模数转换器

    公开(公告)号:US20070268172A1

    公开(公告)日:2007-11-22

    申请号:US11804946

    申请日:2007-05-21

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: H03M1/12

    CPC分类号: H03M1/502 H03M1/14 H03M1/60

    摘要: In a semiconductor-integrated A/D converter, a pulse delay circuit is provided with a plurality of delay units. The plurality of delay units each includes at least one logic gate and operates based on a level of an input signal. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on the level of the input signal. The at least one logic gate is composed of at least one first transistor. The at least one first transistor has a first threshold voltage. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number. The generating circuit is composed of at least one second transistor. The at least one second transistor has a second threshold voltage. The first threshold voltage of the at least one first transistor is lower than the second threshold voltage of the at least one second transistor.

    摘要翻译: 在半导体集成A / D转换器中,脉冲延迟电路具有多个延迟单元。 多个延迟单元各自包括至少一个逻辑门并且基于输入信号的电平进行操作。 脉冲延迟电路被配置为在脉冲信号被多个延迟单元延迟的同时通过多个延迟单元传送脉冲信号。 多个延迟单元中的每一个的延迟时间取决于输入信号的电平。 至少一个逻辑门由至少一个第一晶体管组成。 所述至少一个第一晶体管具有第一阈值电压。 发电电路被配置为获得脉冲信号在预定时间段内通过的多个延迟单元,以基于获得的数量生成数字数据。 发电电路由至少一个第二晶体管构成。 所述至少一个第二晶体管具有第二阈值电压。 所述至少一个第一晶体管的第一阈值电压低于所述至少一个第二晶体管的第二阈值电压。

    A/D converter that is implemented using only digital circuit components and digital signal processing
    44.
    发明申请
    A/D converter that is implemented using only digital circuit components and digital signal processing 有权
    仅使用数字电路元件和数字信号处理实现的A / D转换器

    公开(公告)号:US20060290555A1

    公开(公告)日:2006-12-28

    申请号:US11442127

    申请日:2006-05-30

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: H03M1/12

    摘要: A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

    摘要翻译: A / D转换器的TAD(时间模拟/数字)型具有多个串联连接的延迟单元,每个延迟单元根据转换器输入电压的电平产生延迟,第一级延迟单元在开始时接收脉冲信号 每个A / D转换采样间隔,以及锁存/编码器电路,检测由采样间隔结束时由脉冲信号穿过的延迟单元的总数,以获得表示输入电压电平的数值。 为了确保延迟单元的延迟的均匀性,它们使用比其他电路(例如锁存/编码器电路)的晶体管更大尺寸的晶体管来形成。

    Method of testing A/D converter circuit and A/D converter circuit
    45.
    发明申请
    Method of testing A/D converter circuit and A/D converter circuit 有权
    A / D转换电路和A / D转换电路的测试方法

    公开(公告)号:US20060238394A1

    公开(公告)日:2006-10-26

    申请号:US11407211

    申请日:2006-04-20

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: H03M1/10

    摘要: For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.

    摘要翻译: 用于测试包括由多个级联连接的延迟单元构成的脉冲延迟电路的A / D转换器电路,以及编码电路,被配置为对在预定测量时间内输入脉冲信号通过的延迟单元的数量进行计数;以及 为了输出表示所述计数的数字信号,所述方法包括以下步骤:将所述A / D转换电路设定为测试时间设定在短的测试使用采样周期的测试模式,将所述输入脉冲信号施加到 串行延迟块,每个延迟块由预定数量的延迟单元构成,并且基于从编码电路输出的数字信号确定A / D转换器电路的好坏,所述数字信号表示延迟单元的数量, 输入脉冲信号已通过每个串行延迟块。

    Quadrature detection method, quadrature detection device and radio wave time piece
    46.
    发明申请
    Quadrature detection method, quadrature detection device and radio wave time piece 有权
    正交检测方法,正交检测装置和无线电波时间片

    公开(公告)号:US20060222109A1

    公开(公告)日:2006-10-05

    申请号:US11392966

    申请日:2006-03-30

    IPC分类号: H04L27/22 H04L27/00

    摘要: A radio wave timepiece A and a quadrature detection device for executing a quadrature detecting method are disclosed including a receiving antenna 14 for receiving a carrier wave of a long wave standard radio wave on which time information is multiplexed, a quadrature detection circuit 18 for performing quadrature detection of the carrier wave in response to a reference clock CK1, commonly used for timekeeping by a time counter 8, to obtain an in-phase component I and a quadrature component Q of the carrier wave for obtaining an amplitude AN,m of the carrier wave, and a time correction means 22, 24, 26 for obtaining time information depending on the amplitude of the carrier wave from the quadrature detection circuit 18. The time counter 8 is responsive to time information delivered from the time correction means to correct current time.

    摘要翻译: 公开了一种用于执行正交检测方法的无线电波时钟A和正交检测装置,包括用于接收时间信息被多路复用的长波标准无线电波的载波的接收天线14,用于执行正交的正交检测电路18 响应于通过时间计数器8计时的基准时钟CK 1来检测载波,以获得用于获得振幅A N的载波的同相分量I和正交分量Q ,m +以及用于根据来自正交检测电路18的载波的幅度获得时间信息的时间校正装置22,24,26。 时间计数器8响应于从时间校正装置传递的时间信息来校正当前时间。

    Synchronous detection method and device, and sensor signal detector

    公开(公告)号:US07068744B2

    公开(公告)日:2006-06-27

    申请号:US10216980

    申请日:2002-08-12

    申请人: Takamoto Watanabe

    发明人: Takamoto Watanabe

    IPC分类号: H03D1/04

    摘要: The present invention is intended to efficiently minimize high-frequency noise stemming from synchronous detection without the necessity of a low-pass filter that requires a large time constant. A vibratory gyroscope includes a synchronous detection unit that detects a sense signal sent from a sensing element using a reference signal synchronous with a monitor signal. In the vibratory gyroscope, an analog moving-average filter that produces a moving average of the detection signal by sampling the detection signal during one cycle of the reference signal is used to remove high-frequency noise components from the detection signal, which is detected to be synchronous with the reference signal, without the necessity of a CR filter that requires a large time constant. Consequently, unnecessary noise components whose frequencies are equal to the frequency of the reference signal and those of its harmonics, and which stem from synchronous detection, can be efficiently attenuated owing to an infinite attenuation frequency band offered by the analog moving-average filter.

    Filtering method and A/D conversion apparatus having filtering function
    48.
    发明授权
    Filtering method and A/D conversion apparatus having filtering function 有权
    具有滤波功能的滤波方法和A / D转换装置

    公开(公告)号:US06653964B2

    公开(公告)日:2003-11-25

    申请号:US10207434

    申请日:2002-07-29

    IPC分类号: H03M112

    摘要: In an A/D conversion apparatus comprising an A/D converter (4) and a digital moving average filter (6) for removing high-frequency signal components, there is provided an analog moving average filter (2) at a first stage. A sampling frequency of the filters (6 and 2) is set to fsd=n×fsa (where n is a positive integer of 1, 2, ---). As a result, it becomes possible to superimpose an unnecessary signal passing area that appears at every frequency of n times the sampling frequency fsd in the filter (6), on an area of infinite attenuation that appears at every frequency of n times the sampling frequency fsa in the filter (2). In the apparatus as a whole, it becomes possible to efficiently attenuate unnecessary high-frequency signal components. It is also possible to obtain a similar effect when a time A/D converter is used in place of the analog moving average filter (2) and the A/D converter (4).

    摘要翻译: 在包括用于去除高频信号分量的A / D转换器(4)和数字移动平均滤波器(6)的A / D转换装置中,在第一级提供模拟移动平均滤波器(2)。 滤波器(6和2)的采样频率被设置为fsd = nxfsa(其中n是1,2,...的正整数)。 结果,可以将在滤波器(6)中的采样频率fsd的n倍的每个频率出现的不必要的信号通过区域叠加在出现在采样频率的n倍的每个频率的无限衰减区域 fsa在过滤器(2)中。 在整个装置中,可以有效地衰减不必要的高频信号分量。 当使用时间A / D转换器代替模拟移动平均滤波器(2)和A / D转换器(4)时,也可以获得类似的效果。

    Physical quantity detecting apparatus
    50.
    发明授权
    Physical quantity detecting apparatus 失效
    物理量检测装置

    公开(公告)号:US5812427A

    公开(公告)日:1998-09-22

    申请号:US634254

    申请日:1996-04-18

    IPC分类号: G01D5/24 G01P15/125 G01P15/13

    摘要: A physical amount detecting apparatus, preferably, an acceleration sensor, includes a sensor element, an A/D converter, a control unit and an activation unit. The sensor element is activated by a supply voltage and outputs an electric signal in accordance with a predetermined physical amount. The A/D converter digitizes an analog electric signal and outputs digital data. The control unit calculates a control amount in order to control the sensor element, as the electric signal is set to a predetermined output, based on the digital data, and generates a control signal in accordance with the control amount. The activation unit activates the sensor element in accordance with the control signal. As a result, the control unit outputs a detecting signal indicating a physical amount in accordance with the control amount or the control signal.

    摘要翻译: 优选地,加速度传感器的物理量检测装置包括传感器元件,A / D转换器,控制单元和激活单元。 传感器元件由电源电压激活,并根据预定的物理量输出电信号。 A / D转换器对模拟电信号进行数字化并输出数字数据。 控制单元基于数字数据,计算控制量,以便根据数字数据将电信号设置为预定的输出来控制传感器元件,并根据控制量生成控制信号。 激活单元根据控制信号启动传感器元件。 结果,控制单元根据控制量或控制信号输出指示物理量的检测信号。