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    Semiconductor device including multi-layer conductive thin film of polycrystalline material
    42.
    发明授权
    Semiconductor device including multi-layer conductive thin film of polycrystalline material 失效
    半导体器件包括多层导电薄膜的多晶材料

    公开(公告)号：US5444302A

    公开(公告)日：1995-08-22

    申请号：US168506

    申请日：1993-12-22

    申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

    发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

    IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L29/49 ,  H01L23/48 ,  H01L29/46

    CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004

    摘要： In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

    摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的硅6氧化膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成栅电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

    Copper alloy for an electronic device and method of preparing the same
    44.
    发明授权
    Copper alloy for an electronic device and method of preparing the same 失效
    电子器件用铜合金及其制备方法

    公开(公告)号：US4950451A

    公开(公告)日：1990-08-21

    申请号：US326645

    申请日：1989-03-21

    申请人： Takashi Nakajima ,  Kenji Kubozono ,  Takefumi Itou ,  Kimio Hashizume ,  Shinichi Iwase

    发明人： Takashi Nakajima ,  Kenji Kubozono ,  Takefumi Itou ,  Kimio Hashizume ,  Shinichi Iwase

    IPC分类号： C22C9/04 ,  C22C9/06

    CPC分类号： C22C9/06 ,  C22C9/04

    摘要： A copper alloy for an electronic device comprises 1.0 wt %-4.0 wt % of Ni, more than 0.2 wt % and less than 0.8 wt % of P, 0.5 wt %-6.0 wt % of Zn and the rest being copper and unavoidable impurities. The rest may include 0.05 wt %-1.0 wt % of Mg.A wire of the above-mentioned copper alloy is prepared by heating the copper alloy having the composition described above at temperature of 750.degree. C.-950.degree. C. for more than one minute before the final rolling operation, and then, heating the material at a temperature of 350.degree. C.-500.degree. C., or slowly cooling it at a rate of 4.degree. C./min. or less, or cooling it at a rate of 1.degree. C./min. or more until temperature reaches 500.degree. C. and keeping its temperature for at least one hour in a temperature range of 500.degree. C.-350.degree. C.

    摘要翻译： 用于电子器件的铜合金包括1.0重量％-4.0重量％的Ni，大于0.2重量％且小于0.8重量％的P，0.5重量％-6.0重量％的Zn，其余为铜和不可避免的杂质。 其余的可以包括0.05wt％-1.0wt％的Mg。 通过在最终轧制操作之前将具有上述组成的铜合金在750℃-950℃的温度下加热超过1分钟来制备上述铜合金的线材，然后加热材料 在350℃-500℃的温度下，或以4℃/ min的速度缓慢冷却。 或更低，或以1℃/ min的速率冷却。 或更高，直到温度达到500℃，并将其温度保持在500℃-350℃的温度范围内至少1小时。

    Clock supply device and transmission device
    46.
    发明授权
    Clock supply device and transmission device 有权
    时钟供应装置和传输装置

    公开(公告)号：US08223772B2

    公开(公告)日：2012-07-17

    申请号：US12693436

    申请日：2010-01-25

    申请人： Takashi Nakajima ,  Akio Morimoto ,  Kazunori Kawabe ,  Tatsuru Iwaoka

    发明人： Takashi Nakajima ,  Akio Morimoto ,  Kazunori Kawabe ,  Tatsuru Iwaoka

    IPC分类号： H04L12/28

    CPC分类号： H04J3/0644 ,  H04J3/0685 ,  H04L7/033

    摘要： A clock supply device includes a receiving unit configured to receive frame synchronization packets from an asynchronous network and generate timing signals; a phase comparing unit configured to perform phase comparison by comparing phases of the timing signals generated by the receiving unit and clock signals generated by an internal oscillating unit; a phase variation detection unit configured to detect a frequency variation of the frame synchronization packets based on a trend of a variation amount of a phase difference that is obtained by performing a statistical process on count values obtained as a result of the phase comparison; and an oscillating frequency control unit configured to control an oscillating frequency of the internal oscillating unit when the phase variation detection unit detects the frequency variation of the frame synchronization packets.

    摘要翻译： 时钟提供装置包括：接收单元，被配置为从异步网络接收帧同步分组并产生定时信号; 相位比较单元，被配置为通过比较由接收单元生成的定时信号的相位和由内部振荡单元生成的时钟信号来执行相位比较; 相位变化检测单元，其被配置为基于通过对作为相位比较的结果获得的计数值执行统计处理获得的相位差的变化量的趋势来检测帧同步分组的频率变化; 以及振荡频率控制单元，被配置为当相位变化检测单元检测到帧同步分组的频率变化时，控制内部振荡单元的振荡频率。

    INPUT APPARATUS AND INPUT METHOD
    47.
    发明申请
    INPUT APPARATUS AND INPUT METHOD 有权
    输入装置和输入方法

    公开(公告)号：US20120158332A1

    公开(公告)日：2012-06-21

    申请号：US13305920

    申请日：2011-11-29

    申请人： Satoshi Sakurai ,  Takashi Nakajima ,  Norio Endo

    发明人： Satoshi Sakurai ,  Takashi Nakajima ,  Norio Endo

    IPC分类号： G01R27/08 ,  G06F19/00

    CPC分类号： G06F3/045 ,  G06F3/0416

    摘要： A disclosed input apparatus includes an operating part pressed by a user; a first resistance film and a second resistance film facing each other; a measuring unit configured to measure a difference between a first electric potential of a first end of a contact resistance and a second electric potential of a second end of the contact resistance; and a detecting unit configured to obtain pressure information indicative of a pressure load caused by the pressing of the operating part based on the difference in electric potential.

    摘要翻译： 所公开的输入装置包括由用户按压的操作部分; 第一电阻膜和第二电阻膜彼此面对; 测量单元，被配置为测量接触电阻​​的第一端的第一电位和所述接触电阻的第二端的第二电位之间的差; 以及检测单元，被配置为基于所述电位差获得指示由所述操作部的按压引起的压力负荷的压力信息。

    Coordinate detecting device
    48.
    发明授权
    Coordinate detecting device 有权
    坐标检测装置

    公开(公告)号：US07825906B2

    公开(公告)日：2010-11-02

    申请号：US11442223

    申请日：2006-05-30

    申请人： Takashi Nakajima ,  Koichi Kondoh

    发明人： Takashi Nakajima ,  Koichi Kondoh

    IPC分类号： G06F3/041

    CPC分类号： G06F3/045 ,  G06F2203/04113

    摘要： A coordinate detecting device is disclosed. The coordinate detecting device includes a resistance film, a common electrode which applies electric potential to the resistance film, a voltage supplying section which supplies a voltage to the common electrode, wiring which supplies the voltage to the voltage supplying section, an insulation film disposed between the common electrode and the resistance film, and an electric potential supplying section formed in the insulation film for supplying the electric potential from the common electrode to the resistance film. The coordinate detecting device detects a coordinate of a position on a panel when a user touches the position while an electric potential distribution is generated in the resistance film by being applied electric potential from the common electrode.

    摘要翻译： 公开了一种坐标检测装置。 坐标检测装置包括电阻膜，向电阻膜施加电位的公共电极，向公共电极施加电压的电压供给部，向电压供给部供给电压的配线，配置在电压膜之间的绝缘膜 公共电极和电阻膜，以及形成在绝缘膜中的用于将电位从公共电极提供给电阻膜的电位供应部。 当用户通过从公共电极施加电位在电阻膜中产生电位分布而触摸该位置时，坐标检测装置检测面板上的位置的坐标。

    High-speed pcr using high-speed dna polymerase
    50.
    发明申请
    High-speed pcr using high-speed dna polymerase 审中-公开
    高速pcr使用高速dna聚合酶

    公开(公告)号：US20100203594A1

    公开(公告)日：2010-08-12

    申请号：US11596929

    申请日：2005-05-12

    申请人： Masaya Segawa ,  Takashi Nakajima ,  Masanori Oka

    发明人： Masaya Segawa ,  Takashi Nakajima ,  Masanori Oka

    IPC分类号： C12P19/34 ,  C12N9/10

    CPC分类号： C12Q1/686 ,  C12N9/1252 ,  C12Q2527/113

    摘要： [Problems] To achieve a high-speed PCR which can be completed in a period of several minutes and thus can be used for a new application.[Means for Solving Problems] A method for practicing a high-speed PCR under a temperature change of 10° C./sec or more, characterized in that use is made of a heat-resistant DNA polymerase exhibiting a speed of synthesizing a deoxyribonucleic acid of 100 base/sec or higher, and a reagent kit for a high-speed PCR, or use in the method.

    摘要翻译： [问题]实现可以在几分钟内完成的高速PCR，因此可以用于新的应用。 解决问题的手段在10℃/秒以上的温度变化下进行高速PCR的方法，其特征在于，使用具有合成脱氧核糖核酸速度的耐热DNA聚合酶 100碱基/秒以上，以及用于高速PCR的试剂盒，或者在该方法中使用。