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276 条记录 (耗时 0.025 秒)

    Semiconductor memory device
    41.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5508970A

    公开(公告)日：1996-04-16

    申请号：US345682

    申请日：1994-11-21

    申请人： Haruki Toda

    发明人： Haruki Toda

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C8/04

    CPC分类号： G11C7/1051 ,  G11C7/1006 ,  G11C7/103

    摘要： A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a"-units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.

    摘要翻译： 一种具有存储单元阵列（MCA）的半导体存储器件，具有以包括多列的矩阵模式布置的多个存储单元组成的数据寄存器单元，具有两个第一和第二寄存器，每个寄存器具有“a” - 一个单位 位数据寄存器; 控制部分，用于根据输入和读取的地址从每个“a”的多个列中选择列的两组“a”组，并且用于存储“a” 根据读取地址的顺序交替地选择第一和第二寄存器中的任一个寄存器中的列“2”一个“一列” 以及数据输出部分，用于依次扫描和输出一位数据寄存器的2“a”个数据的数据。 尽管最小的寄存器配置，列位数大于寄存器数量的数据可以连续访问。 此外，可以自由选择头列地址。

    Clock-synchronous semiconductor memory device and method for accessing the device
    42.
    发明授权
    Clock-synchronous semiconductor memory device and method for accessing the device 失效
    时钟同步半导体存储器件和用于访问器件的方法

    公开(公告)号：US5323358A

    公开(公告)日：1994-06-21

    申请号：US024354

    申请日：1993-03-01

    申请人： Haruki Toda ,  Yuji Watanabe ,  Hitoshi Kuyama ,  Shozo Saito

    发明人： Haruki Toda ,  Yuji Watanabe ,  Hitoshi Kuyama ,  Shozo Saito

    IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/22

    摘要： A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.

    摘要翻译： 一种用于访问包括以矩阵布置的存储单元的时钟同步半导体存储器件的方法。 单元被划分为至少两个块，从外部设备提供的地址数据指定对这些块中的单元的访问，并且与外部提供的时钟信号同步地执行对存储单元的访问，其中包括设置另一个 在一个块处于访问操作状态时处于访问准备状态或访问操作待机状态的块，当通过地址指定特定块进行访问操作时，经由访问准备状态将某个块设置在访问操作状态 数据，并且如果某个块处于访问操作状态，并且当特定块被地址数据指定用于访问操作时，并且特定块处于访问准备状态时，立即将某个块设置在访问操作状态，或者 在访问操作待机状态。 在设备中，使用指定从设备外部提供的块的地址数据来设置要访问的块中的小区的指定。

    Image memory
    43.
    发明授权
    Image memory 失效
    图像存储器

    公开(公告)号：US5185724A

    公开(公告)日：1993-02-09

    申请号：US586232

    申请日：1990-09-21

    申请人： Haruki Toda

    发明人： Haruki Toda

    IPC分类号： G11C11/401 ,  G06F12/02 ,  G06F12/04 ,  G06T1/60 ,  G11C7/10

    CPC分类号： G11C7/1075

    摘要： An image memory comprises a random access memory, a serial access memory including a main register and a preregister, a data transfer section for carrying out data transfer between the random access memory and the serial access memory, and a designation section for designating an address of serial access. The data transfer section serves to transfer data from the random access memory to the main register of the serial access memory through the preregister. Furthermore, a serial access to the serial access memory is made on the basis of an address designated by the designation means. Thus, a transfer system defined as a hidden transfer for carrying out data transfer only between the random access memory and the preregister is set as a technique for relaxing the restriction on the transfer timings. This technique permits the serial access memory to be used with the divided or split segments having arbitrary lengths, respectively.

    Semiconductor memory device with column redundancy
    44.
    发明授权
    Semiconductor memory device with column redundancy 失效
    具有列冗余的半导体存储器件

    公开(公告)号：US5168468A

    公开(公告)日：1992-12-01

    申请号：US789036

    申请日：1991-11-07

    申请人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

    发明人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/818

    摘要： A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.

    摘要翻译： 半导体存储器件包括存储单元阵列，冗余存储单元阵列，位线对，备用位线对，列存储有故障单元的列地址的信息和备用列列地址的列地址信息存储电路 单元，列解码器，用于连接位线对和第一数据输出线对中的一个的第一列选择栅极，用于连接位线对之一和第二数据输出线对的第二列选择栅极，备用列解码器 用于选择第三或第四列选择线，用于连接备用位线对和第一数据输出线对的第三列选择栅极，用于连接备用位线对和第二数据输出线对的第四列选择栅极 用于选择两个数据并放大和输出的第一缓冲器，用于放大和输出来自第二数据输出线对的数据的第二缓冲器，以及用于存储 控制来自第一和/或第二缓冲器的数据。

    Semiconductor memory system
    45.
    发明授权
    Semiconductor memory system 失效
    半导体存储系统

    公开(公告)号：US5107464A

    公开(公告)日：1992-04-21

    申请号：US480902

    申请日：1990-02-16

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

    Semiconductor memory device
    46.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5095463A

    公开(公告)日：1992-03-10

    申请号：US586217

    申请日：1990-09-21

    申请人： Haruki Toda ,  Mitsugi Ogura

    发明人： Haruki Toda ,  Mitsugi Ogura

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/403 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

    摘要： A novel semiconductor memory device having address comparator, word line drive circuit sense circuit, and control circuit is disclosed. The comparator judges whether or not a row address read in the present access cycle is in correspondence with that in the last cycle. Where it is judged that the former is not in correspondence with the latter, the control circuit allows the sense circuit to select a word line by this row address to transfer data of a memory cell to the bit line to allow the sense means to sense. On the other hand, where it is judged by the comparator that the former is in correspondence with the latter, since data of the memory cell belonging to the same word line is already sensed in the last cycle, the control circuit allows the readout circuit to read out data from a bit line corresponding to the column address without causing the sense circuit to carry out a sense operation for a second time. Thus, only when the row address changes with respect to that in the last cycle, a sense operation is caused to be carried out. Thus, the readout operation can be performed at a high speed.

    Flip-flop circuit
    48.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4678934A

    公开(公告)日：1987-07-07

    申请号：US884629

    申请日：1986-07-11

    申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

    CPC分类号： H03K3/356026 ,  G11C8/06

    摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

    摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

    Semiconductor memory device executing a write operation with first and second voltage applications
    50.
    发明授权
    Semiconductor memory device executing a write operation with first and second voltage applications 有权
    半导体存储器件利用第一和第二电压应用执行写操作

    公开(公告)号：US09245621B2

    公开(公告)日：2016-01-26

    申请号：US14118703

    申请日：2012-03-09

    申请人： Jun Deguchi ,  Haruki Toda

    发明人： Jun Deguchi ,  Haruki Toda

    IPC分类号： G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/77

    摘要： A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.

    摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括设置在多个第一线和多条第二线的交点处的多个存储单元; 和写电路。 写入电路在执行写入操作时执行第一步骤，跨连接到数据写入目标的选择的存储器单元的第一和第二线路施加电压，并跨越连接到第一和第二线路的不同电压 所述多个存储单元的数据写未指定的未选择的存储单元，并且在执行所述第一步骤之后，执行第二步骤，在连接到所选存储单元的第一和第二行上施加数据写入所需的电压 并且将连接到未选择的存储单元的第一和第二线中的至少一个引入浮动状态。