公开(公告)号：US20140120711A1

公开(公告)日：2014-05-01

申请号：US13661998

申请日：2012-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun

IPC: H01L21/283

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

Abstract: Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition.

Abstract translation: 提供一种形成金属栅极的方法，包括以下步骤。 在衬底上形成介电层，其中在电介质层中形成栅极沟槽，并且在栅极沟槽中形成栅极电介质层。 通过在物理气相沉积期间在靶和衬底之间施加AC偏压，在栅极沟槽中形成第一金属层。 通过在物理气相沉积期间在靶和衬底之间施加DC偏压，在栅极沟槽中形成第二金属层。

公开(公告)号：US20140097507A1

公开(公告)日：2014-04-10

申请号：US14105198

申请日：2013-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Chin-Fu Lin ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chien-Hao Chen

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L21/28026 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 提供基板，并且在其上形成栅极电介质和功函数金属层，其中功函数金属层在栅极电介质层上。 然后，在功函数金属层上形成顶部阻挡层。 形成顶部阻挡层的步骤包括增加顶部阻挡层中边界保护材料的浓度。 最后，在顶部阻挡层上形成金属层。 本发明还提供一种具有金属栅极的半导体器件。

公开(公告)号：US20230238445A1

公开(公告)日：2023-07-27

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/7786 ,  H01L21/76841 ,  H01L21/3245

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20220238632A1

公开(公告)日：2022-07-28

申请号：US17160319

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chi-Mao Hsu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Hsin-Fu Huang

IPC: H01L49/02 ,  H01C7/00 ,  H01C17/08

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

公开(公告)号：US11239243B2

公开(公告)日：2022-02-01

申请号：US16866573

申请日：2020-05-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

公开(公告)号：US20210351347A1

公开(公告)日：2021-11-11

申请号：US17384817

申请日：2021-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US20200350317A1

公开(公告)日：2020-11-05

申请号：US16931397

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10756090B2

公开(公告)日：2020-08-25

申请号：US15922899

申请日：2018-03-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L21/8242 ,  H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US20200168450A1

公开(公告)日：2020-05-28

申请号：US16203212

申请日：2018-11-28

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Kuan-Hsiang Chen ,  Hsin-Fu Huang ,  Chun-Ling Lin ,  Sheng-Yi Su ,  Pei-Hsun Kao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.

公开(公告)号：US20190229014A1

公开(公告)日：2019-07-25

申请号：US15888069

申请日：2018-02-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kuan-Chun Lin ,  Hsin-Fu Huang ,  Wei-Chih Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: A method for fabricating a semiconductor structure is disclosed. A bit line is formed on a substrate. The bit line comprises a tungsten layer and cap layer on the tungsten layer. A low-temperature physical vapor deposition (PVD) process is performed to deposit a silicon nitride spacer layer covering the bit line and the substrate. The silicon nitride spacer layer is in direct contact with the tungsten layer. The low-temperature PVD process is performed at a temperature ranging between 200˜400° C.