公开(公告)号：US10199228B2

公开(公告)日：2019-02-05

申请号：US15479292

申请日：2017-04-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

摘要： A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US20150061042A1

公开(公告)日：2015-03-05

申请号：US14016234

申请日：2013-09-03

申请人： UNITED MICROELECTRONICS CORP.

发明人： Tsun-Min Cheng ,  Nien-Ting Ho ,  Chien-Hao Chen ,  Ching-Yun Chang ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chi-Yuan Sun ,  Chi-Mao Hsu

IPC分类号： H01L29/49 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/285

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.

摘要翻译： 提供了金属栅极结构。 金属栅极结构包括半导体衬底，栅极电介质层，多层P型功函数层和导电金属层。 栅极电介质层设置在半导体衬底上。 多层P型功函数层设置在栅极电介质层上，多层P型功函数层至少包含结晶P型功函数层和至少一非晶P型功函数层 层。 此外，导电性金属层设置在多层P型功函数层上。

公开(公告)号：US09653300B2

公开(公告)日：2017-05-16

申请号：US13864218

申请日：2013-04-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC分类号： H01L27/148 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US08735269B1

公开(公告)日：2014-05-27

申请号：US13741402

申请日：2013-01-15

申请人： United Microelectronics Corp.

发明人： Chi-Yuan Sun ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chin-Fu Lin

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

摘要： The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

摘要翻译： 形成半导体结构的方法包括首先提供衬底。 然后，以0.3〜0.8埃的速度在基板上形成TiN层。 最后，直接在TiN层上形成多晶硅层。 由于阻挡层中的TiN以低的速率形成以获得良好的质量，因此可以避免TiN层中的缺陷或上层的缺陷，例如栅极虚设层或栅极盖层。

公开(公告)号：US20140346616A1

公开(公告)日：2014-11-27

申请号：US14454727

申请日：2014-08-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

摘要翻译： 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140239419A1

公开(公告)日：2014-08-28

申请号：US13778227

申请日：2013-02-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Nien-Ting Ho ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC分类号： H01L29/423 ,  H01L29/40

CPC分类号： H01L29/401 ,  H01L21/28044 ,  H01L21/28185 ,  H01L29/4925 ,  H01L29/51

摘要： A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.

摘要翻译： 提供一种制造半导体器件的方法。 提供硅衬底，并且在硅衬底上形成栅极绝缘层。 然后，通过物理气相沉积（PVD）工艺在栅极绝缘层上形成硅阻挡层。 接着，在硅阻隔层上形成含硅层。 本实施方式的硅阻隔层是基本上为氢的氢浓度为零的氢 - 实际为零的硅层。

公开(公告)号：US20170207093A1

公开(公告)日：2017-07-20

申请号：US15479292

申请日：2017-04-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US09076784B2

公开(公告)日：2015-07-07

申请号：US14454727

申请日：2014-08-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

摘要翻译： 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140306273A1

公开(公告)日：2014-10-16

申请号：US13864218

申请日：2013-04-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC分类号： H01L21/28 ,  H01L29/423

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

摘要翻译： 提供了金属栅极结构的制造方法。 首先，提供由层间电介质覆盖的基板。 在层间电介质中形成栅极沟槽，其中在栅极沟槽中形成栅极电介质层。 在栅极沟槽中的栅极电介质层上形成含硅功函数层。 最后，栅极沟槽填充有导电金属层。

公开(公告)号：US20140120711A1

公开(公告)日：2014-05-01

申请号：US13661998

申请日：2012-10-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun

IPC分类号： H01L21/283

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition.

摘要翻译： 提供一种形成金属栅极的方法，包括以下步骤。 在衬底上形成介电层，其中在电介质层中形成栅极沟槽，并且在栅极沟槽中形成栅极电介质层。 通过在物理气相沉积期间在靶和衬底之间施加AC偏压，在栅极沟槽中形成第一金属层。 通过在物理气相沉积期间在靶和衬底之间施加DC偏压，在栅极沟槽中形成第二金属层。