公开(公告)号：US10256340B2

公开(公告)日：2019-04-09

申请号：US15140780

申请日：2016-04-28

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yu-Lung Chin ,  Shin-Cheng Lin ,  Wen-Hsin Lin ,  Cheng-Tsung Wu

IPC: H01L29/94 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/761 ,  H01L29/06 ,  H01L29/10

Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region having a second conductivity type therein. An epitaxial layer is on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer on the first doping region. A second doping region and a third doping region that have the second conductivity type are respectively in the epitaxial layer on both opposite sides of the body region, so as to adjoin the body region. Source and drain regions are respectively in the body region and the second doping region. A field insulating layer is in the second doping region between the source and drain regions. A gate structure is on the epitaxial layer to cover a portion of the field insulating layer.

公开(公告)号：US10181512B2

公开(公告)日：2019-01-15

申请号：US15866583

申请日：2018-01-10

Applicant: Vanguard International Semiconductor Corporation

Inventor： Wen-Hsin Lin ,  Shin-Cheng Lin ,  Cheng-Tsung Wu ,  Yu-Hao Ho

IPC: H01L21/337 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225

Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.

公开(公告)号：US10002956B1

公开(公告)日：2018-06-19

申请号：US15692415

申请日：2017-08-31

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Hsin-Chih Lin ,  Yung-Hao Lin ,  Chia-Ching Huang

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/12 ,  H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/122 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7785

Abstract: A high electron mobility transistor includes a buffer layer disposed on a substrate. A barrier layer is disposed on the buffer layer. A channel layer is disposed in the buffer layer and is adjacent to the interface between the buffer layer and the barrier layer. A gate electrode is disposed on the barrier layer. A drain electrode is disposed on the barrier layer on a first side of the gate electrode. A source electrode is disposed on the barrier layer on a second side of the gate electrode. A first enhancement layer is disposed on the barrier layer and the channel layer between the gate electrode and the drain electrode and is not in direct contact with the gate electrode, the source electrode, or the drain electrode. The first enhancement layer is an N-type doped III-V semiconductor.

公开(公告)号：US09608107B2

公开(公告)日：2017-03-28

申请号：US14192097

申请日：2014-02-27

Applicant: Vanguard International Semiconductor Corporation

Inventor： Tsung-Hsiung Lee ,  Shin-Cheng Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/66659 ,  H01L21/265 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

公开(公告)号：US09559200B2

公开(公告)日：2017-01-31

申请号：US15052624

申请日：2016-02-24

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shang-Hui Tu ,  Chih-Jen Huang ,  Jui-Chun Chang ,  Shin-Cheng Lin ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/70 ,  H01L21/265 ,  H01L21/266 ,  H01L29/423

CPC classification number: H01L29/7801 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract translation: 提供半导体器件。 该器件包括具有第一导电类型的衬底。 该器件还包括漏极区域，源极区域和设置在衬底中的阱区域。 阱区域设置在漏极区域和源极区域之间并且具有与第一导电类型相反的第二导电类型。 该器件还包括设置在阱区内的多个掺杂区域。 掺杂区域彼此垂直和水平地偏移。 每个掺杂区域包括具有第一导电类型的下部分和堆叠在下部区域上并具有第二导电类型的上部。

公开(公告)号：US09455345B2

公开(公告)日：2016-09-27

申请号：US15007465

申请日：2016-01-27

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Shang-Hui Tu ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract translation: 提供半导体器件。 半导体器件包括设置在衬底上的第一导电类型的衬底和第一导电类型的外延结构。 半导体器件还包括设置在外延结构中的第一导电类型的第一掺杂浓度和衬底的阱区。 半导体器件还包括分别形成在阱区内部和外部的外延结构中的漏极区域和源极区域。 半导体器件还包括设置在源极区域下方的第一导电类型的主体区域和布置在漏极区域和源极区域之间的阱区域中的一对第一和第二掺杂区域。 第一和第二掺杂区域延伸到阱区域的外部并朝着身体区域延伸。

公开(公告)号：US09269808B2

公开(公告)日：2016-02-23

申请号：US14186530

申请日：2014-02-21

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Shang-Hui Tu ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

公开(公告)号：US09129989B1

公开(公告)日：2015-09-08

申请号：US14692413

申请日：2015-04-21

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shang-Hui Tu ,  Chih-Jen Huang ,  Jui-Chun Chang ,  Yu-Hao Ho ,  Wen-Hsin Lin ,  Shin-Cheng Lin

IPC: H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7816 ,  H01L21/32139 ,  H01L29/0611 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.

公开(公告)号：US20240243194A1

公开(公告)日：2024-07-18

申请号：US18098079

申请日：2023-01-17

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Chia-Ching Huang

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/66462

Abstract: A high electron mobility transistor structure includes a compound semiconductor channel layer disposed on a substrate, a compound semiconductor barrier layer disposed on the compound semiconductor channel layer, and a compound semiconductor cap layer disposed on the compound semiconductor barrier layer. The compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and a gap between the first segment and the second segment. A gate electrode is disposed on the compound semiconductor cap layer. A source electrode and a drain electrode are disposed on the compound semiconductor barrier layer, arranged along a second direction and respectively located on two sides of the compound semiconductor cap layer.

公开(公告)号：US11670708B2

公开(公告)日：2023-06-06

申请号：US17032977

申请日：2020-09-25

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Chih-Yen Chen ,  Chia-Ching Huang

IPC: H01L29/778 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L29/1025

Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.