公开(公告)号：US5989623A

公开(公告)日：1999-11-23

申请号：US914521

申请日：1997-08-19

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  B05D5/12

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76807

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US5763010A

公开(公告)日：1998-06-09

申请号：US646862

申请日：1996-05-08

申请人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

发明人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

IPC分类号： C23C16/40 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  B05D3/02 ,  B05D1/36 ,  H05H1/24

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/56 ,  G06Q30/0284 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76828

摘要： A method of stabilizing a halogen-doped silicon oxide film to reduce halogen atoms migrating from said film during subsequent processing steps. A halogen-doped film is deposited over a substrate and then subjected to a degassing step in which the film is briefly heated to a temperature of between about 300.degree. and 550.degree. C. before deposition of a diffusion barrier layer. It is believed that such a heat treatment step removes loosely bonded halogen atoms from the halogen-doped film and thus the treatment is referred to as a degassing step. In a preferred version of this embodiment, the halogen-doped silicon oxide film is an FSG film that is subjected to a degassing treatment for between about 35 and 50 seconds.

摘要翻译： 一种稳定卤素掺杂氧化硅膜以减少在后续处理步骤中从所述膜迁移的卤素原子的方法。 将卤素掺杂的膜沉积在衬底上，然后进行脱气步骤，其中在沉积扩散阻挡层之前将膜短暂加热至约300℃至550℃的温度。 据信这样的热处理步骤从卤素掺杂的膜去除松散键合的卤素原子，因此将该处理称为脱气步骤。 在该实施方案的优选方案中，卤素掺杂氧化硅膜是经过脱气处理约35至50秒的FSG膜。