公开(公告)号：US6079354A

公开(公告)日：2000-06-27

申请号：US65758

申请日：1998-04-24

申请人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

发明人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

IPC分类号： C23C16/40 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  C23C16/00 ,  G06F19/00

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/56 ,  G06Q30/0284 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76828

摘要： A method of stabilizing a halogen-doped silicon oxide film to reduce halogen atoms migrating from said film during subsequent processing steps. A halogen-doped film is deposited over a substrate and then subjected to a degassing step in which the film is briefly heated to a temperature of between about 300 and 550.degree. C. before deposition of a diffusion barrier layer. It is believed that such a heat treatment step removes loosely bonded halogen atoms from the halogen-doped film and thus the treatment is referred to as a degassing step. In a preferred version of this embodiment, the halogen-doped silicon oxide film is an FSG film that is subjected to a degassing treatment for between about 35 and 50 seconds.

摘要翻译： 一种稳定卤素掺杂氧化硅膜以减少在后续处理步骤中从所述膜迁移的卤素原子的方法。 将卤素掺杂的膜沉积在衬底上，然后进行脱气步骤，其中在沉积扩散阻挡层之前将膜短暂加热至约300至550℃之间的温度。 据信这样的热处理步骤从卤素掺杂的膜去除松散键合的卤素原子，因此将该处理称为脱气步骤。 在该实施方案的优选方案中，卤素掺杂氧化硅膜是经过脱气处理约35至50秒的FSG膜。

公开(公告)号：US5763010A

公开(公告)日：1998-06-09

申请号：US646862

申请日：1996-05-08

申请人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

发明人： Ted Guo ,  Barney M. Cohen ,  Amrita Verma

IPC分类号： C23C16/40 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  B05D3/02 ,  B05D1/36 ,  H05H1/24

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/56 ,  G06Q30/0284 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76828

摘要： A method of stabilizing a halogen-doped silicon oxide film to reduce halogen atoms migrating from said film during subsequent processing steps. A halogen-doped film is deposited over a substrate and then subjected to a degassing step in which the film is briefly heated to a temperature of between about 300.degree. and 550.degree. C. before deposition of a diffusion barrier layer. It is believed that such a heat treatment step removes loosely bonded halogen atoms from the halogen-doped film and thus the treatment is referred to as a degassing step. In a preferred version of this embodiment, the halogen-doped silicon oxide film is an FSG film that is subjected to a degassing treatment for between about 35 and 50 seconds.

摘要翻译： 一种稳定卤素掺杂氧化硅膜以减少在后续处理步骤中从所述膜迁移的卤素原子的方法。 将卤素掺杂的膜沉积在衬底上，然后进行脱气步骤，其中在沉积扩散阻挡层之前将膜短暂加热至约300℃至550℃的温度。 据信这样的热处理步骤从卤素掺杂的膜去除松散键合的卤素原子，因此将该处理称为脱气步骤。 在该实施方案的优选方案中，卤素掺杂氧化硅膜是经过脱气处理约35至50秒的FSG膜。

公开(公告)号：US07824743B2

公开(公告)日：2010-11-02

申请号：US11864100

申请日：2007-09-28

申请人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

发明人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

IPC分类号： B05D5/12 ,  H01L21/04 ,  H01L21/203 ,  H05H1/24

CPC分类号： H01J37/34 ,  C23C14/0036 ,  C23C14/0089 ,  C23C14/0641 ,  H01J37/32449 ,  H01J37/32706 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments described herein provide a method for forming two titanium nitride materials by different PVD processes, such that a metallic titanium nitride layer is initially formed by a PVD process in a metallic mode and a titanium nitride retarding layer is formed over a portion of the metallic titanium nitride layer by a PVD process in a poison mode. Subsequently, a first aluminum layer, such as an aluminum seed layer, may be selectively deposited on exposed portions of the metallic titanium nitride layer by a CVD process. Thereafter, a second aluminum layer, such as an aluminum bulk layer, may be deposited on exposed portions of the first aluminum layer and the titanium nitride retarding layer during an aluminum PVD process.

摘要翻译： 本文所述的实施例提供了通过不同PVD工艺形成两种氮化钛材料的方法，使得最初通过金属模式的PVD工艺形成金属氮化钛层，并且在金属钛的一部分上形成氮化钛延迟层 氮化物层通过PVD工艺处于毒液模式。 随后，通过CVD工艺可以在金属氮化钛层的暴露部分上选择性地沉积第一铝层，例如铝籽晶层。 此后，在铝PVD工艺期间，可以在第一铝层和氮化钛延迟层的暴露部分上沉积第二铝层，例如铝本体层。

公开(公告)号：US20060144703A1

公开(公告)日：2006-07-06

申请号：US11029641

申请日：2005-01-05

申请人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

发明人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

IPC分类号： C23C14/00

CPC分类号： H01J37/3408 ,  H01J37/3405

摘要： A multi-track magnetron having a convolute shape and asymmetric about the target center about which it rotates. A plasma track is formed as a closed loop between opposed inner and outer magnetic poles, preferably as two or three radially arranged and spirally shaped counter-propagating tracks with respect to the target center and preferably passing over the rotation axis. The pole shape may be optimized to produce a cumulative track length distribution conforming to the function L=arn. After several iterations of computerized optimization, the pole shape may be tested for sputtering uniformity with different distributions of magnets in the fabricated pole pieces. If the uniformity remains unsatisfactory, the design iteration is repeated with a different n value, different number of tracks, or different pole widths. The optimization reduces azimuthal sidewall asymmetry and improves radial deposition uniformity.

摘要翻译： 具有卷绕形状且围绕其旋转的目标中心不对称的多轨磁控管。 等离子体轨道形成为相对的内部和外部磁极之间的闭合回路，优选地相对于目标中心并且优选地通过旋转轴线而形成为两个或三个径向布置且螺旋形的反向传播轨迹。 极点形状可以被优化以产生符合函数L = ar 的累积轨迹长度分布。 经过数次迭代的计算机化优化，可以测试极点形状，使其在制造的极片中具有不同的磁体分布的溅射均匀性。 如果均匀性不能令人满意，则使用不同的n值，不同数量的轨道或不同的极宽重复设计迭代。 优化可减少方位角侧壁不对称性，提高径向沉积均匀性。

公开(公告)号：US06605531B1

公开(公告)日：2003-08-12

申请号：US09127010

申请日：1998-07-31

申请人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

发明人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

IPC分类号： H01L214763

CPC分类号： H01L21/2855 ,  H01L21/28556 ,  H01L21/76882

摘要： The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.

摘要翻译： 本发明提供了一种通过在基板上沉积不足厚度的金属膜来填充基板上的孔的方法，以填充次半微米孔径，然后在低压室内在低于熔点的温度下将基板退火 沉积金属膜。 本发明还提供了通过在退火膜上物理气相沉积金属膜而在无空隙孔上形成平坦化膜。

公开(公告)号：US06528180B1

公开(公告)日：2003-03-04

申请号：US09577705

申请日：2000-05-23

申请人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

发明人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

IPC分类号： H01L2940

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12611 ,  Y10T428/12743 ,  Y10T428/12806 ,  Y10T428/26

摘要： A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.

摘要翻译： 公开了一种金属化集成电路的方法。 在一个方面，集成电路通过将衬垫材料沉积在衬底上而后接一个或多个金属层进行金属化。 衬垫材料选自钽（Ta），氮化钽（TaN），铌（Nb），氮化铌（NbN），钒（V），氮化钒（VN）及其组合。 优选使用物理气相沉积（PVD）将衬垫材料适当地沉积在衬底上。 使用化学气相沉积（CVD），物理气相沉积（PVD）或CVD和PVD的组合将一个或多个金属层沉积在阻挡层上。

公开(公告)号：US06169030A

公开(公告)日：2001-01-02

申请号：US09007233

申请日：1998-01-14

申请人： Mehul B. Naik ,  Ted Guo ,  Liang-Yuh Chen ,  Roderick Craig Mosely ,  Israel Beinglass

发明人： Mehul B. Naik ,  Ted Guo ,  Liang-Yuh Chen ,  Roderick Craig Mosely ,  Israel Beinglass

IPC分类号： H01L2144

CPC分类号： C23C14/32 ,  C23C14/025 ,  C23C14/046 ,  H01L21/2855 ,  H01L21/76877

摘要： The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.

摘要翻译： 本发明通常提供了一种改进的方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在高纵横比，半微米应用中形成连续的无空隙互连。 本发明提供了一种多步骤PVD工艺，其中等离子体功率对于每个步骤而言是变化的，以获得良好的填充特性以及良好的反射率，形态和产量。 初始等离子体功率相对较低，以确保孔的良好的无空隙填充，然后增加等离子体功率以获得期望的反射率和形态特征。 本发明提供一种孔填充方法，其包括在物理气相沉积中物理气相沉积衬底上的金属并改变等离子体功率。 优选地，等离子体功率从第一离散低等离子体功率变化到第二离散高等离子体功率。 更优选地，等离子体功率从第一离散低等离子体功率变化到第二离散低等离子体功率到第三离散高等离子体功率。

公开(公告)号：US6110828A

公开(公告)日：2000-08-29

申请号：US791653

申请日：1996-12-30

申请人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan

发明人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan

IPC分类号： H01L21/285 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/443

CPC分类号： H01L21/76879

摘要： The present invention generally provides a method of forming a structure having a selective CVD metal plug with a continuous barrier layer formed thereon. More particularly, the present invention applies a thin layer of warm PVD metal over a selective CVD metal plug and adjacent nodules on the dielectric field to planarize the metal surface. A barrier is then deposited over the planarized metal surface. Therefore, the invention provides the advantages of having (1) void-free, sub-half micron selective CVD metal via plugs and interconnects, and (2) a reduced number of process steps without the use of CMP, and (3) barrier layers over the metal plugs to improve the electromigration resistance of the metal.

摘要翻译： 本发明通常提供一种形成具有在其上形成有连续势垒层的选择性CVD金属塞的结构的方法。 更具体地说，本发明在选择性CVD金属塞上和在电介质场上的相邻结节上施加薄层的温热PVD金属以使金属表面平坦化。 然后在平坦化的金属表面上沉积屏障。 因此，本发明提供了具有（1）无空隙的半微米选择性CVD金属通孔塞和互连件的优点，和（2）减少数量的工艺步骤而不使用CMP，以及（3）阻挡层 在金属插头上提高金属的电迁移阻力。

公开(公告)号：US20080308416A1

公开(公告)日：2008-12-18

申请号：US11764772

申请日：2007-06-18

申请人： Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

发明人： Adolph Miller Allen ,  Ki Hwan Yoon ,  Ted Guo ,  Hong S. Yang ,  Sang-Ho Yu

IPC分类号： C23C14/34

CPC分类号： C23C14/3407 ,  H01J37/3423 ,  H01J37/3435

摘要： A sputtering target for a sputtering chamber comprises a backing plate with a sputtering plate mounted thereon. In one version, the backing plate comprises a circular plate having a front surface comprising an annular groove. The sputtering plate comprises a disk comprising a sputtering surface and a backside surface having a circular ridge that is shaped and sized to fit into the annular groove of the backing plate.

摘要翻译： 用于溅射室的溅射靶包括安装有溅射板的背板。 在一个版本中，背板包括具有包括环形凹槽的前表面的圆形板。 溅射板包括包括溅射表面的圆盘和具有圆形脊的后侧表面，该圆形脊的形状和尺寸适于装配到背板的环形槽中。

公开(公告)号：US07378002B2

公开(公告)日：2008-05-27

申请号：US11209328

申请日：2005-08-23

申请人： Wei Ti Lee ,  Ted Guo ,  Sang-Ho Yu

发明人： Wei Ti Lee ,  Ted Guo ,  Sang-Ho Yu

IPC分类号： C23C14/35 ,  H01L21/44

CPC分类号： C23C14/185 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345

摘要： An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter reactors. The first step includes sputtering a high fraction of ionized aluminum atoms onto a relatively cold wafer, e.g., held at less than 150° C., and relatively highly biased to attract aluminum atoms into the narrow holes and etch overhangs. The second step includes more neutral sputtering onto a relatively warm wafer, e.g. held at greater than 250° C., and substantially unbiased to provide a more isotropic and uniform aluminum flux. The magnetron scanned about the back of the aluminum target may be relatively small and unbalanced in the first step and relatively large and balanced in the second.

摘要翻译： 一种铝溅射工艺，包括RF偏置晶片和两步铝填充工艺和装置，用于在两个明显不同的条件下，优选在两个不同的等离子体溅射反应器中通过溅射将铝填充到窄通孔中。 第一步包括将大部分电离铝原子溅射到相对冷的晶片上，例如保持在小于150℃，并且相当高的偏压以将铝原子吸引到窄孔中并蚀刻突出端。 第二步包括在相对温暖的晶片上的更中性的溅射，例如 保持在大于250℃，并且基本上无偏差以提供更多的各向同性和均匀的铝通量。 围绕铝靶的背面扫描的磁控管可能在第一步骤中相对较小并且不平衡，而在第二步中相对较大且平衡。