公开(公告)号：US07667261B2

公开(公告)日：2010-02-23

申请号：US11785382

申请日：2007-04-17

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07652318B2

公开(公告)日：2010-01-26

申请号：US11592290

申请日：2006-11-03

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07385244B2

公开(公告)日：2008-06-10

申请号：US11051845

申请日：2005-02-03

申请人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

摘要翻译： 一种在多晶硅蚀刻工艺中形成改进的蚀刻硬掩模氧化物层的方法，包括提供包括相邻的第一裸露多晶硅部分和暴露的氧化物部分的平坦化的半导体晶片工艺表面; 选择性地蚀刻暴露的氧化物部分的厚度部分; 在暴露的多晶硅部分上热生长氧化物硬掩模层以形成氧化物硬掩模部分; 暴露出与至少一个氧化物硬掩模部分相邻的第二暴露的多晶硅部分; 并且蚀刻穿过第二暴露的多晶硅部分的厚度部分。

公开(公告)号：US20070205436A1

公开(公告)日：2007-09-06

申请号：US11368714

申请日：2006-03-06

申请人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

发明人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

摘要翻译： 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

公开(公告)号：US07106629B2

公开(公告)日：2006-09-12

申请号：US10788949

申请日：2004-02-27

申请人： Wen-Ting Chu ,  Chia-Ta Hsieh

发明人： Wen-Ting Chu ,  Chia-Ta Hsieh

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The split-gate, P-channel structure, which includes a P+ drain, P+ source, floating gate and a control gate, advantageously improves protection from over-erase and hot-hole trap conditions, and improves programming speed and higher injection efficiency. The cell is erased by a polysilicon-polysilicon tunneling technique.

摘要翻译： 定义了具有带 - 带热电子（BBHE）编程方法的分裂门P通道快闪存储器单元，以提高电池性能的耐久特性。 包括P +漏极，P +源极，浮动栅极和控制栅极的分离栅极P沟道结构有利地提高了对过度擦除和热阱阱条件的保护，并提高了编程速度和更高的注入效率。 电池被多晶硅多晶硅隧道技术擦除。

公开(公告)号：US20060170029A1

公开(公告)日：2006-08-03

申请号：US11045850

申请日：2005-01-28

申请人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.

摘要翻译： 一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。 在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。 可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。 然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。 在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。 电介质层被部分蚀刻以形成介电层的多个厚度。 去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

公开(公告)号：US07030444B2

公开(公告)日：2006-04-18

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US20050112828A1

公开(公告)日：2005-05-26

申请号：US10719722

申请日：2003-11-21

申请人： Wen-Ting Chu ,  Shih-Chang Liu

发明人： Wen-Ting Chu ,  Shih-Chang Liu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.

摘要翻译： 实现了在制造集成电路器件中形成晶体管栅极的新方法。 该方法包括提供基底。 导体层形成在衬底之上，其间具有介电层。 形成覆盖在导体层上的掩模层。 形成覆盖掩模层的抗蚀剂层。 图案化抗蚀剂层，从而选择性地暴露掩模层。 抗蚀剂层在抗蚀剂层的边缘之间呈现第一间隔。 暴露的掩模层被蚀刻通过，从而选择性地暴露导体层。 掩模层的蚀刻边缘是锥形的，使得掩模层在导体层的顶表面处的掩模层边缘之间呈现第二间隔。 第二个间距小于第一个间距。 蚀刻暴露的导体层从而完成晶体管栅极。

公开(公告)号：US6110782A

公开(公告)日：2000-08-29

申请号：US195651

申请日：1998-11-19

申请人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chon Ho ,  Chang-Song Lin ,  Di-Son Kwo

发明人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chon Ho ,  Chang-Song Lin ,  Di-Son Kwo

IPC分类号： H01L21/8234 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/823462 ,  H01L27/11541

摘要： A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在单个晶片上制造高电压和低压器件中的自对准硅化物和高电压器件工艺的集成方法。 在半导体衬底上形成隔离区域，该半导体衬底围绕低电压器件区域和高电压器件区域电隔离。 在器件区域中生长栅极氧化物层。 沉积覆盖栅极氧化物层和隔离区的多晶硅层。 第一光掩模形成在高电压器件区域的一部分上，其中第一光掩模也完全覆盖低电压器件区域。 多晶硅层被蚀刻掉，其未被光掩模覆盖以形成高压器件。 植入离子以在与高压器件相邻的半导体衬底内形成轻掺杂的源极和漏极区，其中第一光掩模保护低电压器件区域中的多晶硅层与离子。 第一个光掩模被删除。 第二光掩模形成在要形成栅电极的低电压器件区域的一部分上，其中第二光掩模也完全覆盖高电压器件区域。 蚀刻掉未被第二光掩模覆盖的多晶硅层以形成栅电极。 第二个光掩模被删除。 低电压和高电压区域的器件被硅化，并且完成了集成电路器件的制造。

公开(公告)号：US08780628B2

公开(公告)日：2014-07-15

申请号：US13241932

申请日：2011-09-23

申请人： Yvonne Lin ,  Wen-Ting Chu

发明人： Yvonne Lin ,  Wen-Ting Chu

IPC分类号： G11C16/04

CPC分类号： H01L27/0805 ,  G11C16/0408 ,  G11C16/08 ,  G11C29/82 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/11526 ,  H01L28/60 ,  H01L29/94

摘要： An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes.

摘要翻译： 集成电路包括至少一个闪存阵列和设置在衬底上的至少一个电容器阵列。 所述至少一个电容器阵列包括多个电容器单元结构。 电容器单元结构各自包括设置在基板上的第一电容器电极。 第二电容器电极设置在第一电容器电极上。 第三电容器电极设置成与第一和第二电容器电极的第一侧壁相邻。 第四电容器电极设置成与第一和第二电容器电极的第二侧壁相邻。