-
公开(公告)号：US5615207A
公开(公告)日：1997-03-25
申请号：US482045
申请日：1995-06-07
IPC分类号： H04L12/46
CPC分类号： H04L12/4616
摘要： A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path. Also provided is a method of communicating information from a sending communication device to a target communication device, comprising the steps of a) determining if the target communication device is on a local bus corresponding to the sending communication device, b) transferring the information from the sending communication device to the target communication device on the local bus corresponding to the sending communication device if the result of step a) is that the target communication device is on the local bus corresponding to the sending communication device, c) transferring the information from the sending communication device to an express bus if the result of step a) is that the target communication device is not on the local bus corresponding to the sending communication device, d) transferring the information from the express bus to a local bus corresponding to the target communication device, and e) transferring the information from the local bus corresponding to the target communication device to the target communication device.
摘要翻译： 数据通信系统包括快速总线，多个本地总线和多个本地/快速桥接器，每个本地/快速桥接器将相应的本地总线连接到快速总线。 多个本地/本地桥接器每个连接两个相应的本地总线。 多个本地总线和多个本地/本地桥接器包括本地路径。 还提供了一种从发送通信设备向目标通信设备传送信息的方法，包括以下步骤：a）确定目标通信设备是否在与发送通信设备相对应的本地总线上，b）将信息从 如果步骤a）的结果是目标通信设备在与发送通信设备相对应的本地总线上，则将通信设备发送到与发送通信设备相对应的本地总线上的目标通信设备，c）将信息从 如果步骤a）的结果是目标通信设备不在与发送通信设备相对应的本地总线上，则将通信设备发送到快速总线，d）将信息从快速总线传送到与目标对应的本地总线 通信设备，以及e）从与ta相对应的本地总线传送信息 rget通信设备到目标通信设备。
-
公开(公告)号：US5218681A
公开(公告)日：1993-06-08
申请号：US576061
申请日：1990-08-31
CPC分类号： G06F13/4027 , G06F13/14
摘要： An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection. Further, in the preferred embodiment of the present invention, the supplemental processing circuit generates an intervention signal in response to the local processing unit, the buffer circuit responding to the intervention signal by configuring appropriately to provide operative access by the apparatus of the second data bus.
-
43.发明申请Systems and Methods for Booting a Codec Processor over a High Definition Audio Bus 有权通过高清晰度音频总线引导编解码器处理器的系统和方法公开(公告)号：US20090063843A1
公开(公告)日：2009-03-05
申请号：US12202359
申请日：2008-09-01
IPC分类号： G06F15/177
CPC分类号： G06F9/4401 , G06F9/4408
摘要： Systems and methods for booting a programmable processor such as a DSP that is incorporated into an HDA codec. The codec and a system memory containing boot program instructions are connected to an HDA bus. In a first mode, the DSP receives boot program instructions via the HDA bus and boots using these instructions. In a second mode, the DSP boots from instructions that are contained in a memory that is connected to the DSP. In one embodiment, the memory connected to the DSP is a component of a plug-in card, and the DSP is configured to determine whether the plug-in card is present, then boot from the memory on the plug-in card if it is present or boot from the system memory via the HDA bus if the plug-in card is not present.
摘要翻译： 用于引导可编程处理器（例如并入HDA编解码器的DSP）的系统和方法。 编解码器和包含引导程序指令的系统存储器连接到HDA总线。 在第一种模式下，DSP通过HDA总线接收引导程序指令，并使用这些指令进行引导。 在第二种模式下，DSP从包含在连接到DSP的存储器中的指令引导。 在一个实施例中，连接到DSP的存储器是插件卡的组件，并且DSP被配置为确定插件卡是否存在，然后从插件卡上的存储器引导，如果它是 如果插件卡不存在，则通过HDA总线从系统存储器中显示或引导。
-
44.发明授权System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus 失效用于重新启动外设总线时钟信号并请求掌握外设总线的系统和方法
公开(公告)号：US06163848A
公开(公告)日：2000-12-19
申请号：US125406
申请日：1993-09-22
CPC分类号： G06F1/3215
摘要： A system and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus are provided that accommodate a power conservation technique in which a peripheral bus clock signal may be stopped. If an alternate bus master requires mastership of the peripheral bus when the peripheral bus clock signal is stopped, the alternate bus master asserts a clock request signal for re-starting the peripheral bus clock. The clock request signal is broadcasted on the peripheral bus and is accordingly received by a clock control circuit. The clock control circuit responsively causes the re-starting of the peripheral bus clock signal. Subsequently, the alternate bus master can generate a bus request signal that is synchronous to the peripheral bus clock signal to thereby obtain a grant signal from a bus arbiter unit. As a result, the peripheral bus clock signal can be stopped for power management while still accommodating alternate bus masters that must assert a synchronous bus request signal to obtain mastership of the peripheral bus.
摘要翻译： 提供了一种用于重新启动外围总线时钟信号并请求掌握外围总线的系统和方法，其适应可以停止外围总线时钟信号的功率节省技术。 当外设总线时钟信号停止时，如果备用总线主机需要外部总线的掌握，则备用总线主机会断言重新启动外设总线时钟的时钟请求信号。 时钟请求信号在外设总线上广播，因此由时钟控制电路接收。 时钟控制电路响应地引起外部总线时钟信号的重新启动。 随后，备用总线主机可以产生与外围总线时钟信号同步的总线请求信号，从而从总线仲裁器单元获得授权信号。 因此，外围总线时钟信号可以停止以进行电源管理，同时仍然容纳必须断言同步总线请求信号的备用总线主机以获得外围总线的掌握。
-
45.发明授权Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。 用于引用中断请求的中断请求标识代码按其优先顺序存储。 每个嵌套缓冲区只需要等于优先级数量的条目数。
-
46.发明授权Interrupt controller with external in-service indication for power management within a computer system 失效具有外部在线指示的中断控制器，用于计算机系统内的电源管理
公开(公告)号：US5894577A
公开(公告)日：1999-04-13
申请号：US125336
申请日：1993-09-22
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译： 中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。 还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。 提供在线寄存器用于存储由微处理器服务的任何请求线的标识。 在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。 功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。 使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。 通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。
-
47.发明授权Interrupt controller optimized for power management in a computer system or subsystem 失效针对计算机系统或子系统中的电源管理优化的中断控制器
公开(公告)号：US5765003A
公开(公告)日：1998-06-09
申请号：US671831
申请日：1996-10-09
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译： 中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。 还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。 提供在线寄存器用于存储由微处理器服务的任何请求线的标识。 在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。 功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。 使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。 通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。
-
公开(公告)号：US5640573A
公开(公告)日：1997-06-17
申请号：US190280
申请日：1994-02-02
CPC分类号： G06F1/3203
摘要： An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an outside power management unit. The power management message bus is channeled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor. By providing encoded information regarding the internal events of the integrated processor, monitoring of such events by an external power management unit is possible while the number of external pins on the integrated processor are minimized.
摘要翻译： 提供了一种集成处理器，其包括耦合到诸如DMA控制器，中断控制器和定时器的各种片上外围设备的CPU核心。 集成处理器还包括耦合到DMA控制器，中断控制器和用于监视集成处理器的内部中断和总线请求信号的定时器的电源管理消息单元。 功率管理消息单元还可以根据系统要求监视集成处理器的其他选定的活动。 根据检测到的活动（如果有的话），功率管理消息单元对功率管理消息总线上的消息进行编码，从而向外部电源管理单元提供关于集成处理器的内部事件的信息。 电源管理消息总线从与集成处理器的标准外部外围总线隔离的一组封装引脚从集成处理器引导。 通过提供关于集成处理器的内部事件的编码信息，可以在集成处理器上的外部引脚的数量最小化的同时由外部电源管理单元监视这种事件。
-
49.发明授权System management mode and in-circuit emulation memory mapping and locking method 失效系统管理模式和在线仿真存储器映射和锁定方法
公开(公告)号：US5623673A
公开(公告)日：1997-04-22
申请号：US279474
申请日：1994-07-25
CPC分类号： G06F11/3652
摘要： A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code. If, however, the SMM interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts an ICE interrupt signal which causes the microprocessor core to commence executing the SMM code. Both the SMM code and ICE code may be mapped within a region of system memory which is common to the mapping of a video controller.
摘要翻译： 提供了一种包括中断驱动的系统管理模式的计算机系统，在该模式期间访问系统管理代码。 在一个实施例中，提供锁定寄存器以在计算机系统以其正常模式操作时防止对系统管理代码的访问。 在一个实施例中，中断控制单元耦合到微处理器核心的ICE中断线，并且根据外部“调试”中断信号和外部SMM（系统管理模式）中断信号的断言来控制存储器控制单元。 如果调试中断信号在微处理器内核工作在正常模式时被置位，则中断控制单元响应地将ICE中断信号置为微处理器内核，从而使微处理器内核执行ICE代码。 然而，如果在微处理器内核工作在正常模式时SMM中断信号被置位，则中断控制单元响应地断言ICE中断信号，使得微处理器核心开始执行SMM代码。 SMM代码和ICE代码都可以被映射到系统存储器的区域中，这对于视频控制器的映射是共同的。
-
50.发明授权Integrated digital processing apparatus having a single biodirectional data bus for accommodating a plurality of peripheral devices connected to a plurality of external buses 失效具有用于容纳连接到多个外部总线的多个外围设备的单个双向数据总线的集成数字处理设备
公开(公告)号：US5369777A
公开(公告)日：1994-11-29
申请号：US71940
申请日：1993-06-03
CPC分类号： G06F15/7842 , G06F13/4027 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： An integrated digital processing apparatus for use in a computing device. The apparatus comprises a central processor for effecting processing functions according to a program, a plurality of bus-accommodating devices for accommodating direct operative connection of peripheral devices via a plurality of buses, a single internal bus for accommodating communications internal of the apparatus among the central processing unit and the plurality of bus-accommodating devices, and an internal bus control for controlling utilization of the internal bus. The apparatus is, preferably, configured as an integrated digital circuit on a single substrate.
摘要翻译： 一种用于计算设备的集成数字处理装置。 该装置包括用于根据程序实现处理功能的中央处理器，用于经由多个总线容纳外围设备的直接操作连接的多个总线容纳设备，用于在中央内部容纳设备内部的通信的单个内部总线 处理单元和多个总线容纳装置，以及用于控制内部总线的利用的内部总线控制。 该装置优选地被配置为在单个基板上的集成数字电路。
-
-
-
-
-
-
-
-
-
搜索结果
50 条记录 (耗时 0.03 秒)
