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1.发明授权Non-volatile memory array controller capable of controlling memory banks having variable bit widths 失效能够控制具有可变位宽度的存储体的非易失性存储器阵列控制器
公开(公告)号：US5630099A
公开(公告)日：1997-05-13
申请号：US166124
申请日：1993-12-10
CPC分类号： G06F13/4018
摘要： A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to store BIOS code, and may be implemented using a ROM or flash memory device. The non-volatile memory controller includes a data router, a sequencer, and a set of output latches for routing the 8-bit BIOS code (stored within the 8-bit bank) to selected byte lanes of the local bus and for converting the 8-bit data to 32-bit local bus data. The non-volatile memory controller further supports high performance, 32-bit accesses to the user software stored within the 32-bit banks. If the system designer or user instead must maximize the memory capacity of the computer system, the 8-bit bank of memory may be replaced with a larger 32-bit bank of memory. In this configuration, a control signal is provided to the non-volatile memory controller to indicate that a 32-bit bank is connected rather than an 8-bit bank. The control signal causes the sequencer and the data router to be disabled. When a memory access to the 32-bit bank is executed, the non-volatile memory controller accesses the data within the 32-bit bank and drives the data directly on the CPU local bus.
摘要翻译： 提供了一种非易失性存储器控制器，其可直接连接到计算机系统的本地总线，并且允许访问一个或多个32位的ROM组和8位非易失性存储器组。 8位非易失性存储器组可以用于例如存储BIOS代码，并且可以使用ROM或闪速存储器件来实现。 非易失性存储器控制器包括数据路由器，定序器和一组输出锁存器，用于将8位BIOS代码（存储在8位存储区中）路由到本地总线的选定字节通道，并用于转换8 位数据传输到32位本地总线数据。 非易失性存储器控制器还支持对存储在32位存储区中的用户软件的高性能32位访问。 如果系统设计人员或用户必须最大化计算机系统的内存容量，则8位存储器组可能会被更大的32位存储器组替换。 在该配置中，向非易失性存储器控制器提供控制信号以指示连接32位存储体而不是8位存储体。 控制信号使定序器和数据路由器被禁用。 当执行对32位存储区的存储器访问时，非易失性存储器控制器访问32位存储区中的数据，并直接在CPU本地总线上驱动数据。
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2.发明授权High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
公开(公告)号：US5557757A
公开(公告)日：1996-09-17
申请号：US190647
申请日：1994-02-02
CPC分类号： G06F13/423 , G06F13/4027
摘要： An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
摘要翻译： 集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。 可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。 集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚 总线上的集成处理器。 辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。 不需要用于辅助总线的集成处理器的独立地址和数据线。 因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。 因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。
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3.发明授权
公开(公告)号：US5768584A
公开(公告)日：1998-06-16
申请号：US710047
申请日：1996-09-10
CPC分类号： G06F9/4401 , G06F12/0653
摘要： A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines. In this configuration, each output line of the decoder is coupled to a respective bank enable input line of the ROM banks. In either configuration, the chip enable lines are driven in a mutually exclusive relationship during system boot to access the boot code (stored within one of the ROM banks). Subsequently, the encoding of the chip enable signals at the chip enable output lines of the memory controller is dependent upon configuration information stored in a configuration register.
摘要翻译： 非易失性存储器芯片使能编码方法允许在公共存储器阵列中存储引导代码和用户应用软件。 芯片使能编码方法还允许在非易失性存储器阵列内提供可变数量的存储体，并且在固件选择阵列配置之前允许系统上电并执行引导代码。 在一个实施例中，存储器控制器包括用于选择性地启用多个ROM组的四个芯片使能输出线。 其中一个ROM库包括在系统引导期间由系统微处理器执行的引导代码。 如果用户需要由四个ROM组组成的ROM阵列，则每个ROM组连接有单独的芯片使能输出线。 如果用户需要由例如八个ROM组组成的ROM阵列，则外部解码器可以连接到四个芯片使能输出线。 在该配置中，解码器的每个输出线耦合到ROM组的相应的bank使能输入线。 在任一配置中，芯片使能线在系统引导期间以相互排斥的关系被驱动以访问引导代码（存储在ROM库之一内）。 随后，存储器控制器的芯片使能输出线处的芯片使能信号的编码取决于存储在配置寄存器中的配置信息。
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公开(公告)号：US5218681A
公开(公告)日：1993-06-08
申请号：US576061
申请日：1990-08-31
CPC分类号： G06F13/4027 , G06F13/14
摘要： An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection. Further, in the preferred embodiment of the present invention, the supplemental processing circuit generates an intervention signal in response to the local processing unit, the buffer circuit responding to the intervention signal by configuring appropriately to provide operative access by the apparatus of the second data bus.
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5.发明授权System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus 失效通过分别在本地总线上驱动DMA配置寄存器的地址和存储地址来执行I / O访问和存储器访问的系统
公开(公告)号：US5561821A
公开(公告)日：1996-10-01
申请号：US145375
申请日：1993-10-29
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.
摘要翻译： 提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。 因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。 不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。 由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。 最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。
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6.发明授权Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller 失效计算机系统在通过在DMA控制器中驱动本地总线上的范围内的地址来禁用非参与的外设的I / O寻址技术期间选择外围设备的字节通道
公开(公告)号：US5561819A
公开(公告)日：1996-10-01
申请号：US145376
申请日：1993-10-29
CPC分类号： G06F13/28 , G06F13/4018
摘要： A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.
摘要翻译： 直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。 外围设备响应地在指定的字节通道处接收或提供数据。 结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。
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7.发明授权Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility 失效电源管理架构，包括用于传送编码的活动信号的电源管理消息总线，以获得最佳的灵活性
公开(公告)号：US5493684A
公开(公告)日：1996-02-20
申请号：US223984
申请日：1994-04-06
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/325 , G06F1/3287 , Y02B60/1217 , Y02B60/1282
摘要： An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit. The power management unit receives the encoded messages on the power management message bus and responsively makes decisions as to the appropriate power management mode to enter. The power management unit includes a clock control unit coupled to an internal clock generator of the integrated processor for controlling the frequencies of a CPU clock signal and a system clock signal. The power management unit further includes a power control unit for controlling the application of power to various external peripheral devices.
摘要翻译： 提供了一种集成处理器，其包括耦合到诸如DMA控制器，中断控制器和定时器的各种片上外围设备的CPU核心。 集成处理器还包括耦合到DMA控制器，中断控制器和用于监视集成处理器的内部中断和总线请求信号的定时器的电源管理消息单元。 功率管理消息单元还可以监视集成处理器的其他选定的活动，例如浮点协处理子单元的活动。 基于所检测到的活动（如果有的话），功率管理消息单元对功率管理消息总线上的消息进行编码，从而向外部电源管理单元提供关于集成处理器的内部事件的信息。 电源管理决定由外部电源管理单元进行。 电源管理单元在电源管理消息总线上接收编码的消息，并且响应于作出关于进入的适当的电源管理模式的决定。 功率管理单元包括时钟控制单元，其耦合到集成处理器的内部时钟发生器，用于控制CPU时钟信号和系统时钟信号的频率。 电源管理单元还包括用于控制向各种外部外围设备施加电力的电力控制单元。
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8.发明授权Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。 用于引用中断请求的中断请求标识代码按其优先顺序存储。 每个嵌套缓冲区只需要等于优先级数量的条目数。
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9.发明授权Interrupt controller optimized for power management in a computer system or subsystem 失效针对计算机系统或子系统中的电源管理优化的中断控制器
公开(公告)号：US5765003A
公开(公告)日：1998-06-09
申请号：US671831
申请日：1996-10-09
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译： 中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。 还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。 提供在线寄存器用于存储由微处理器服务的任何请求线的标识。 在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。 功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。 使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。 通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。
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公开(公告)号：US5640573A
公开(公告)日：1997-06-17
申请号：US190280
申请日：1994-02-02
CPC分类号： G06F1/3203
摘要： An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an outside power management unit. The power management message bus is channeled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor. By providing encoded information regarding the internal events of the integrated processor, monitoring of such events by an external power management unit is possible while the number of external pins on the integrated processor are minimized.
摘要翻译： 提供了一种集成处理器，其包括耦合到诸如DMA控制器，中断控制器和定时器的各种片上外围设备的CPU核心。 集成处理器还包括耦合到DMA控制器，中断控制器和用于监视集成处理器的内部中断和总线请求信号的定时器的电源管理消息单元。 功率管理消息单元还可以根据系统要求监视集成处理器的其他选定的活动。 根据检测到的活动（如果有的话），功率管理消息单元对功率管理消息总线上的消息进行编码，从而向外部电源管理单元提供关于集成处理器的内部事件的信息。 电源管理消息总线从与集成处理器的标准外部外围总线隔离的一组封装引脚从集成处理器引导。 通过提供关于集成处理器的内部事件的编码信息，可以在集成处理器上的外部引脚的数量最小化的同时由外部电源管理单元监视这种事件。
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