公开(公告)号：US11036827B1

公开(公告)日：2021-06-15

申请号：US15786346

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Elliott Delaye ,  Yongjun Wu ,  Aaron Ng ,  Ashish Sirasao ,  Khang K. Dao

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/30

Abstract: Methods and apparatus are described for simultaneously buffering and reformatting (e.g., transposing) a matrix for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). Examples of the present disclosure increase the effective double data rate (DDR) memory throughput for streaming data into GEMM digital signal processing (DSP) engine multifold, as well as eliminate slow data reformatting on a host central processing unit (CPU). This may be accomplished through software-defined (e.g., C++) data structures and access patterns that result in hardware logic that simultaneously buffers and reorganizes the data to achieve linear DDR addressing.

公开(公告)号：US10990826B1

公开(公告)日：2021-04-27

申请号：US16358930

申请日：2019-03-20

Applicant: Xilinx, Inc.

Inventor： Mujib Haider ,  Venkata V. Dhanikonda ,  Ashish Sirasao

IPC: G06K9/00 ,  G06F17/15 ,  G06T7/246 ,  G06N3/04

Abstract: Detecting objects in video may include receiving object detections for a plurality of selected frames of a video from a still image detector, wherein the plurality of selected frames are non-adjacent frames of the video, propagating the object detections from the plurality of selected frames to sequential frames of the video adjacent to the plurality of selected frames based on a distance metric and vector flow data for the sequential frames, suppressing false positive object detections from the propagating, and outputting resulting object detections for the sequential frames of the video.

公开(公告)号：US10990736B1

公开(公告)日：2021-04-27

申请号：US16821465

申请日：2020-03-17

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Satyaprakash Pareek ,  Krishna Garlapati ,  Ashish Sirasao

IPC: G06F30/30 ,  G06F30/337 ,  G06F30/327 ,  G03F1/70 ,  G06F30/31 ,  G06F119/12

Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.

公开(公告)号：US10984500B1

公开(公告)日：2021-04-20

申请号：US16576365

申请日：2019-09-19

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Elliott Delaye ,  Aaron Ng ,  Ehsan Ghasemi

IPC: G06T1/20 ,  H03K19/1776 ,  G06F3/03 ,  G06T1/60 ,  H04N21/2381 ,  H04N5/30 ,  G06F12/00

Abstract: An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; bank address and control circuitry coupled to control inputs of the plurality of memory banks, the multiplexer circuitry, and the first plurality of registers; output control circuitry coupled to control inputs of the second plurality of registers; and a control state machine coupled to the bank address and control circuitry and the output control circuitry.

公开(公告)号：US10943039B1

公开(公告)日：2021-03-09

申请号：US15786105

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Elliott Delaye ,  Sean Settle ,  Zhao Ma ,  Ehsan Ghasemi ,  Xiao Teng ,  Aaron Ng ,  Jindrich Zejda

IPC: G06F30/327 ,  G06F7/544 ,  G06N3/04 ,  G06F30/34

Abstract: An example multiply accumulate (MACC) circuit includes: a multiply-accumulator having an accumulator output register; a quantizer, coupled to the multiply accumulator; and a control circuit coupled to the multiply-accumulator and the quantizer, the control circuit configured to provide control data to the quantizer, the control data indicative of a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register.

公开(公告)号：US10747502B2

公开(公告)日：2020-08-18

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/544 ,  G06F7/499 ,  G06F9/30 ,  G06F9/38

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

公开(公告)号：US20190114535A1

公开(公告)日：2019-04-18

申请号：US15786288

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Ashish Sirasao

IPC: G06N3/063 ,  G06N3/04

Abstract: A disclosed neural network processing system includes a host computer system, a RAMs coupled to the host computer system, and neural network accelerators coupled to the RAMs, respectively. The host computer system is configured with software that when executed causes the host computer system to write input data and work requests to the RAMS. Each work request specifies a subset of neural network operations to perform and memory locations in a RAM of the input data and parameters. A graph of dependencies among neural network operations is built and additional dependencies added. The operations are partitioned into coarse grain tasks and fine grain subtasks for optimal scheduling for parallel execution. The subtasks are scheduled to accelerator kernels of matching capabilities. Each neural network accelerator is configured to read a work request from the respective RAM and perform the subset of neural network operations on the input data using the parameters.

公开(公告)号：US20190114529A1

公开(公告)日：2019-04-18

申请号：US15785800

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Elliott Delaye ,  Ehsan Ghasemi ,  Xiao Teng ,  Jindrich Zejda ,  Yongjun Wu ,  Sean Settle ,  Ashish Sirasao

IPC: G06N3/04

Abstract: In the disclosed methods and systems for processing in a neural network system, a host computer system writes a plurality of weight matrices associated with a plurality of layers of a neural network to a memory shared with a neural network accelerator. The host computer system further assembles a plurality of per-layer instructions into an instruction package. Each per-layer instruction specifies processing of a respective layer of the plurality of layers of the neural network, and respective offsets of weight matrices in a shared memory. The host computer system writes input data and the instruction package to the shared memory. The neural network accelerator reads the instruction package from the shared memory and processes the plurality of per-layer instructions of the instruction package.

公开(公告)号：US09235498B1

公开(公告)日：2016-01-12

申请号：US13908160

申请日：2013-06-03

Applicant: Xilinx, Inc.

Inventor： Jay Southard ,  Krishna Garlapati ,  Elliott Delaye ,  Ashish Sirasao ,  Bing Tian

IPC: G06F12/00

CPC classification number: G11C19/28 ,  G06F17/5054 ,  G11C7/1006 ,  G11C7/1039 ,  H03K5/131 ,  H03K19/1737

Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

Abstract translation: 描述了能够修改输入数据流的电路。 电路包括串联耦合的第一多个寄存器; 耦合以接收所述输入数据流的所述第一多个寄存器的输入寄存器; 所述第一多个寄存器的输出寄存器位于所述第一多个寄存器的一端; 以及控制电路，使得能够在预定时间内产生独立于输入数据流的数据值作为电路的输出。

公开(公告)号：US08769450B1

公开(公告)日：2014-07-01

申请号：US13931621

申请日：2013-06-28

Applicant: Xilinx, Inc.

Inventor： Bing Tian ,  Ashish Sirasao

IPC: G06F9/45

CPC classification number: G06F17/504

Abstract: Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.

Abstract translation: 处理电路设计包括为应用于电路设计的合成流的多个变换中的每一个生成来自变换输入的变换输出。 对于每个变换，变换输入和变换输出表示电路设计。 至少一个电路元件从变换输入改变为变换输出。 对于每个变换，生成变换输入的硬件描述语言表示和变换输出的硬件描述语言表示。 对于每个变换，确定变换输入的硬件描述语言表示是否等同于转换输出的硬件描述语言表示。