3D memory array arranged for FN tunneling program and erase
    41.
    发明授权
    3D memory array arranged for FN tunneling program and erase 有权
    3D存储阵列用于FN隧道编程和擦除

    公开(公告)号:US08203187B2

    公开(公告)日:2012-06-19

    申请号:US12705158

    申请日:2010-02-12

    IPC分类号: H01L29/76

    摘要: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译: 3D存储器件包括半导体主体柱和位线柱的阵列,介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱,提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上,在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

    3D TWO-BIT-PER-CELL NAND FLASH MEMORY
    42.
    发明申请
    3D TWO-BIT-PER-CELL NAND FLASH MEMORY 有权
    3D双比特单片NAND闪存

    公开(公告)号:US20110286283A1

    公开(公告)日:2011-11-24

    申请号:US12785291

    申请日:2010-05-21

    IPC分类号: G11C16/04 H01L21/336

    摘要: A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

    摘要翻译: 描述了一种3D存储器件,其包括具有垂直NAND串结构的相应阵列的底部和顶部存储器立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压,并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

    MEMORY AND MANUFACTURING METHOD THEREOF
    43.
    发明申请
    MEMORY AND MANUFACTURING METHOD THEREOF 有权
    内存及其制造方法

    公开(公告)号:US20110089480A1

    公开(公告)日:2011-04-21

    申请号:US12974093

    申请日:2010-12-21

    IPC分类号: H01L29/792

    摘要: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

    摘要翻译: 提供具有隔离双存储单元的存储器。 第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。 隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。 第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。 第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。 布置在多晶硅层上的字线,第一栅极,第二栅极,第一隔离壁和第二隔离壁电连接到第一栅极,第二栅极和多晶硅层。

    3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE
    44.
    发明申请
    3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE 有权
    3D内存阵列安排FN隧道程序和删除

    公开(公告)号:US20100265773A1

    公开(公告)日:2010-10-21

    申请号:US12705158

    申请日:2010-02-12

    IPC分类号: G11C16/04 H01L21/76

    摘要: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译: 3D存储器件包括半导体主体柱和位线柱的阵列,介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱,提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上,在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    45.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20090140321A1

    公开(公告)日:2009-06-04

    申请号:US11949090

    申请日:2007-12-03

    IPC分类号: H01L29/792 H01L21/283

    CPC分类号: H01L27/11573 H01L21/3144

    摘要: A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.

    摘要翻译: 提供半导体器件及其制造方法。 首先,在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。 接下来,氮化物层被氧化。 氮化物层中的氮化物的一部分移动到第一氧化物层和基底。 氮化物层的上部被转换为上部氧化物层。 然后,除去第二区域中的上氧化物层,氮化物层和第一氧化物层。 其次,在第二区域的基底上生长第二氧化物层。 第二区域中的氮化物移动到第二氧化物层。

    Non-volatile memory
    46.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号:US07511335B2

    公开(公告)日:2009-03-31

    申请号:US11429070

    申请日:2006-05-05

    IPC分类号: H01L29/792

    摘要: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

    摘要翻译: 提供非易失性存储器。 存储器包括衬底,电介质层,导电层,隔离层,掩埋位线,隧道电介质层,电荷俘获层,势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上,势垒介电层设置在电荷俘获层上。 字线设置在基板上,与埋入位线交叉。

    Method for manufacuring semiconductor device
    47.
    发明申请
    Method for manufacuring semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US20070281423A1

    公开(公告)日:2007-12-06

    申请号:US11445870

    申请日:2006-06-02

    IPC分类号: H01L21/336

    摘要: A method for manufacturing a plurality of memory devices and a plurality of high voltage devices on a substrate are provided. The substrate has a memory region and a high voltage region. The method comprises steps of forming a first dielectric layer on the substrate and then performing a thermal process so as to enlarge the thickness of the first dielectric layer in the high voltage region. A buried diffusion region is formed in the substrate in the memory region and a charge trapping layer and a blocking dielectric layer are formed over the substrate in the memory region. A patterned conductive layer is formed over the substrate so as to form gates the memory region and the high voltage region respectively and then a source/drain region is formed adjacent to the gates in the high voltage region in the substrate.

    摘要翻译: 提供了一种用于在基板上制造多个存储器件和多个高电压器件的方法。 衬底具有存储区和高电压区。 该方法包括以下步骤:在衬底上形成第一电介质层,然后进行热处理,以扩大高电压区域中的第一电介质层的厚度。 在存储区中的衬底中形成掩埋扩散区,并且在存储区中的衬底上形成电荷俘获层和阻挡电介质层。 在衬底上形成图案化的导电层,以分别形成存储区域和高电压区域的栅极,然后在衬底中的高电压区域中邻近栅极形成源极/漏极区域。

    SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    48.
    发明申请
    SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体多层结构及其制造方法

    公开(公告)号:US20140042629A1

    公开(公告)日:2014-02-13

    申请号:US13584366

    申请日:2012-08-13

    IPC分类号: H01L23/485 H01L21/28

    摘要: A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.

    摘要翻译: 公开了一种包括多个第一导电层,多个第一绝缘层和第二导电层的半导体多层结构。 第一导电层分开设置。 每个第一导电层具有上表面,与上表面相对的底表面和侧表面。 第一绝缘层围绕第一导电层的外围设备。 每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分,每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面 。 第二导电层覆盖第一导电层和第一绝缘层。

    Semiconductor device and method of fabricating the same
    49.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号:US07754545B2

    公开(公告)日:2010-07-13

    申请号:US11949090

    申请日:2007-12-03

    IPC分类号: H01L21/339 H01L21/84

    CPC分类号: H01L27/11573 H01L21/3144

    摘要: A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.

    摘要翻译: 提供半导体器件及其制造方法。 首先,在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。 接下来,氮化物层被氧化。 氮化物层中的氮化物的一部分移动到第一氧化物层和基底。 氮化物层的上部被转换为上部氧化物层。 然后,除去第二区域中的上氧化物层,氮化物层和第一氧化物层。 其次,在第二区域的基底上生长第二氧化物层。 第二区域中的氮化物移动到第二氧化物层。

    Method for fabricating non-volatile memory
    50.
    发明授权
    Method for fabricating non-volatile memory 有权
    制造非易失性存储器的方法

    公开(公告)号:US07556999B2

    公开(公告)日:2009-07-07

    申请号:US11531007

    申请日:2006-09-12

    IPC分类号: H01L21/8238

    摘要: A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the memory region. Thereafter, a buried diffusion region is formed in the substrate of the memory area. A charge trapping layer and a third insulating layer are formed over the substrate. A gate insulating layer is formed in the second region in the peripheral area, wherein the first thickness is greater than a second thickness after removing the charge trapping layer and third insulating layer on the first and second region in the peripheral area. A conductive layer is formed over the substrate of the memory area and the peripheral area substantially after the gate insulating layer is formed.

    摘要翻译: 一种用于制造具有存储区域和周边区域的存储器的方法包括在周边区域中的第一区域的衬底上形成具有第一厚度的第一栅极绝缘层和在衬底上形成具有第二厚度的第二绝缘层 记忆区域。 此后,在存储区域的基板中形成掩埋扩散区域。 电荷俘获层和第三绝缘层形成在衬底上。 在周边区域的第二区域中形成栅极绝缘层,其中在除去周边区域中的第一和第二区域上的电荷俘获层和第三绝缘层之后,第一厚度大于第二厚度。 在形成栅极绝缘层之后,在存储区域的基板和外围区域上形成导电层。