公开(公告)号：US09082954B2

公开(公告)日：2015-07-14

申请号：US13210020

申请日：2011-08-15

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/16

摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.

摘要翻译： 改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。 例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。 在另一示例中，相变结构围绕电介质结构。 几种变化改善了相变结构和电极之间的接触。

公开(公告)号：US08946671B2

公开(公告)日：2015-02-03

申请号：US10642244

申请日：2003-08-18

申请人： Sheng-Chih Lai ,  Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Sheng-Chih Lai ,  Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： H01L47/00 ,  H01L27/102 ,  H01L21/822 ,  H01L27/06

CPC分类号： H01L27/1021 ,  H01L21/8221 ,  H01L27/0688

摘要： A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers and the logic “0” or “1” is defined by whether there is a dielectric layer on the diode.

摘要翻译： 掩模只读存储器二极管及其制造方法。 掩模只读存储器是通过堆叠多个二极管层形成的高密度三维阵列，并且逻辑“0”或“1”由二极管上是否存在介电层来定义。

公开(公告)号：US20140042382A1

公开(公告)日：2014-02-13

申请号：US13570660

申请日：2012-08-09

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2463 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

摘要： A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.

摘要翻译： 存储器件包括串联布置的第一导体，二极管，存储元件和第二导体。 二极管包括在第一导体上并与之电气连通的第一半导体层。 图案化绝缘层在第一半导体层上具有侧壁。 二极管包括在侧壁的第一部分上并与第一半导体层接触的中间半导体层。 中间半导体层具有比第一半导体层低的载流子浓度，并且可以包括本征半导体。 在侧壁的第二部分上并与中间半导体层接触的第二半导体层具有比中间半导体层更高的载流子浓度。 存储元件电耦合到第二半导体层。 第二导体电耦合到存储元件。

公开(公告)号：US08497705B2

公开(公告)日：2013-07-30

申请号：US12942462

申请日：2010-11-09

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H03K19/094

CPC分类号： G11C13/0004 ,  G11C2013/008 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79

摘要： A programmable logic device has a configurable interconnection coupling logic blocks, where the configurable interconnection has a phase change element with an amorphous region having a variable size to determine the phase change element is open or short. This isolates the programming path from the logic path.

摘要翻译： 可编程逻辑器件具有可配置的互连耦合逻辑块，其中可配置互连具有具有可变大小的非晶区域的相变元件，以确定相变元件是开路或短路。 这将编程路径与逻辑路径隔离。

公开(公告)号：US20130140513A1

公开(公告)日：2013-06-06

申请号：US13310583

申请日：2011-12-02

申请人： Sheng-Chih Lai ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch

发明人： Sheng-Chih Lai ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

摘要： A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.

摘要翻译： 存储器件包括多个侧壁电极，形成在绝缘层中的沟槽的第一侧壁上，在衬底中的触点阵列中的第一多个触点上。 多个侧壁电极接触第一多个触点的相应顶表面。 侧壁电极分别包括氮化钽层，其具有组成为TaxNy，其中y大于x，并且电极材料层具有比氮化钽层更低的电阻率和更低的热阻率。 多个侧壁电极的顶表面接触记忆材料。 第二多个侧壁电极可以形成在沟槽阵列中的第二多个触点上的沟槽的第二侧壁上。

公开(公告)号：US08437192B2

公开(公告)日：2013-05-07

申请号：US12785291

申请日：2010-05-21

申请人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

发明人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

IPC分类号： G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

公开(公告)号：US20130056699A1

公开(公告)日：2013-03-07

申请号：US13670337

申请日：2012-11-06

申请人： HSIANG-LAN LUNG ,  CHUNG HON LAM

发明人： HSIANG-LAN LUNG ,  CHUNG HON LAM

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

摘要翻译： 一种器件包括具有第一区域和第二区域的衬底。 第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。

公开(公告)号：US20120287706A1

公开(公告)日：2012-11-15

申请号：US13103887

申请日：2011-05-09

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： G11C11/46

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C17/16 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： An integrated circuit memory is based on isolation device free memory cells. The memory cells are passively coupled to bit lines and word lines. The memory cells include an anti-fuse element and an element of phase change material in series. A rupture filament through the anti-fuse layer acts as an electrode for the phase change element. Control circuitry is configured to apply bias arrangements for operation of the memory cells, including a first write bias arrangement to induce a volume of the higher resistivity phase in the phase change material establishing a first threshold for the selected memory cell below a read threshold, a second write bias arrangement to induce a larger volume of the higher resistivity phase in phase change material establishing a second threshold for the selected memory cell above the read threshold, and a read bias arrangement to apply the read threshold to the selected memory cell.

摘要翻译： 集成电路存储器是基于隔离器件的空闲存储器单元。 存储单元被动地耦合到位线和字线。 存储单元包括反熔丝元件和相变材料的元件串联。 通过反熔丝层的断裂丝作为相变元件的电极。 控制电路被配置为施加用于存储器单元的操作的偏置布置，包括第一写入偏置布置，以在相变材料中引起较高电阻率相位的体积，以在低于读取阈值的情况下建立所选存储单元的第一阈值， 第二写入偏置布置以在相位改变材料中引起较大体积的较高电阻率相位，以在所述读取阈值之上建立所选择的存储器单元的第二阈值，以及读取偏置布置以将所述读取阈值应用于所选择的存储器单元。

公开(公告)号：US08273598B2

公开(公告)日：2012-09-25

申请号：US13020051

申请日：2011-02-03

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US08263960B2

公开(公告)日：2012-09-11

申请号：US12978846

申请日：2010-12-27

申请人： Hsiang-Lan Lung ,  Chieh-Fang Chen

发明人： Hsiang-Lan Lung ,  Chieh-Fang Chen

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1691

摘要： Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element.

摘要翻译： 描述存储单元以及制造方法。 本文所述的存储单元包括底部电极，覆盖底部电极的顶部电极，具有从底部电极延伸到顶部电极的侧壁的通孔，以及将底部电极电连接到顶部电极的存储元件。 存储元件具有接触通孔侧壁上的电介质侧壁间隔件的外表面，并且包括底部电极上的杆部分和杆部分上的杯部分。 填充材料在由存储元件的杯部的内表面限定的内部内。