公开(公告)号：US20070032071A1

公开(公告)日：2007-02-08

申请号：US11195174

申请日：2005-08-02

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/4763

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成CoSi 2 N的方法，形成场效应晶体管的方法以及形成导电触点的方法。 在一个实施方案中，形成CoSi 2 N的方法包括在含硅衬底上形成包含MSi xSX的基本上非晶层，其中“M”包括至少一些金属其他 比钴。 包含钴的层被沉积在基本上无定形的MSi x x-xml集成层上。 将衬底退火有效地将含钴层的钴扩散通过基本上无定形的含杂质层并与含硅衬底的硅组合以形成CoSi 2 在基本无定形的MSi x x-xml集成层之下。 考虑了其他方面和实现。

公开(公告)号：US20060019475A1

公开(公告)日：2006-01-26

申请号：US11234334

申请日：2005-09-23

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Hu

IPC: H01L21/20

CPC classification number: H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

Abstract: A method of depositing polysilicon includes positioning a substrate within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor to provide a reactive atmosphere under conditions effective to substantially selectively deposit polysilicon on the crystalline region relative to the amorphous region. The reactive atmosphere during the depositing consists essentially of a gaseous silane precursor.

Abstract translation: 沉积多晶硅的方法包括将衬底定位在化学气相沉积反应器内。 衬底具有暴露的基本上结晶的区域和暴露的基本无定形区域。 包含硅的气态前体被供给到化学气相沉积反应器，以在有效地相对于非晶区域在晶体区域上基本上选择性地沉积多晶硅的条件下提供反应性气氛。 沉积期间的反应性气氛基本上由气态硅烷前体组成。

公开(公告)号：US20060019442A1

公开(公告)日：2006-01-26

申请号：US11234328

申请日：2005-09-23

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Hu

IPC: H01L21/8242

CPC classification number: H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.

Abstract translation: 形成电容器的方法包括在衬底上形成第一电容器电极。 在第一电容器电极上形成基本上结晶的电容器电介质层。 具有基本上结晶的电容器电介质层的衬底设置在化学气相沉积反应器内。 这种衬底具有暴露的基本无定形的材料。 包含硅的气态前体在有效基本上选择性地在基本上结晶的电容器电介质层上沉积多晶硅相对于暴露的基本无定形材料的条件下被馈送到化学气相沉积反应器，并且多晶硅形成第二电容器电极。

公开(公告)号：US20050026532A1

公开(公告)日：2005-02-03

申请号：US10931407

申请日：2004-08-31

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01J1/304 ,  H01J9/02 ,  H01J9/12 ,  H01J9/04

CPC classification number: H01J9/025 ,  H01J1/3044 ,  H01J2201/30426

Abstract: Structures and methods to ease electron emission and limit outgassing so as to inhibit degradation to the electron beam of a field emitter device are described. In one method to ease such electron emission, a layer of low relative dielectric constant material is formed under the surface of the field emitter tip. Another method is to coat the field emitter tip with a low relative dielectric constant substance or compound to form a layer and then cover that layer with a thin layer of the material of the field emitter tip.

Abstract translation: 描述了用于缓和电子发射和限制放气以便抑制场发射器件的电子束劣化的结构和方法。 在一种简化这种电子发射的方法中，在场致发射极尖端的表面下形成一层低相对介电常数材料。 另一种方法是用低相对介电常数物质或化合物涂覆场发射器尖端以形成层，然后用场发射器尖端的材料的薄层覆盖该层。

公开(公告)号：US06806573B2

公开(公告)日：2004-10-19

申请号：US09826661

申请日：2001-04-05

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2348

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.

Abstract translation: 通过将合金或复合靶溅射到凹槽中，将合金或复合材料沉积在半导体衬底的凹陷特征中，以形成第一沉积材料层。 第一沉积材料层以低角度和低能量被重新投射，以将第一沉积材料层重新沉积到凹槽的底部上，作为具有不同于第一沉积材料的化学计量的第二沉积材料层。 在另一实施例中，溅射室环境由氩和氮组成。 在又一个实施例中，再溅射步骤之后是沉积具有与第二沉积层不同的化学计量比的至少一层材料，以形成沉积在凹槽中的材料的“分级”化学计量。

公开(公告)号：US06798026B2

公开(公告)日：2004-09-28

申请号：US10231758

申请日：2002-08-29

Applicant: Yongjun Hu ,  Randhir P. S. Thakur ,  Scott DeBoer

Inventor： Yongjun Hu ,  Randhir P. S. Thakur ,  Scott DeBoer

IPC: H01L2976

CPC classification number: H01L21/28052 ,  H01L21/28061 ,  H01L27/10891 ,  H01L29/4941 ,  Y10S257/914 ,  Y10S257/915

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

公开(公告)号：US06614085B2

公开(公告)日：2003-09-02

申请号：US10003522

申请日：2001-10-31

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L310232

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/318 ,  H01L21/32139 ,  H01L27/1462 ,  H01L31/02161 ,  H01L31/02327 ,  Y10S430/151

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns. One preferred material for the inventive antireflective layer includes metal silicon nitride ternary compounds of the general formula MxSiyNz wherein M is at least one transition metal, x is less than y, and z is in a range from about 0 to about 5y. Preferably, the Si will exceed M by about a factor of two. Addition of N is controlled by the ratio in the sputtering gas such as Ar/N. Tungsten is a preferred transition metal in the fabrication of the inventive antireflective coating. A preferred tungsten silicide target will have a composition of silicon between 1 and 4 in stoichiometric ratio to tungsten. Composite antireflective layers made of metal silicide binary compounds or metal silicon nitride ternary compounds may be fashioned according to the present invention depending upon a specific application.

公开(公告)号：US06204171B1

公开(公告)日：2001-03-20

申请号：US08862685

申请日：1997-05-23

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2144

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is a smooth and has large nitride grains of a diffusion barrier material selected from a group consisting of tungsten alloys of Group III and Group IV early transition metals and molybdenum alloys of Group III and Group IV early transition metals. The diffusion barrier material is preferably selected from a group consisting of ScyMz, ZryMz, ZrvScyMz, ZrvNbyMz, ZruScvNbyMz, NbyMz, NbvScyMz, TiyMz, TivScyMz, TivNbyMz, and TivZryMz, where M is one of tungsten and molybdenum. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level wherein primarily the diffusion barrier material is sputtered with between about 4×108 to about 4×1015 nitride nuclei of the diffusion barrier material per cm2 of the diffusion barrier material, where the nitride nucleation of diffusion barrier material is evenly distributed. A grain growth step is then conducted in a nitrogen environment to grow a film of large nitride grain of the diffuision barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal salicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种制造平滑且具有大的氮化物颗粒的方法，所述扩散阻挡材料选自由III族和IV族早期过渡金属的钨合金组成的组和III族和IV族早期过渡金属的钼合金 。 扩散阻挡材料优选选自ScyMz，ZryMz，ZrvScyMz，ZrvNbyMz，ZruScvNbyMz，NbyMz，NbvScyMz，TiyMz，TivScyMz，TivNbyMz和TivZryMz，其中M是钨和钼之一。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境的氮含量，其中主要是扩散阻挡材料溅射，每隔膜扩散阻挡材料的扩散阻挡材料的介于约4×10 8至约4×10 15个氮化物核之间，其中扩散阻挡材料的氮化物成核 均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长分散阻挡材料的大氮化物颗粒的膜。 还公开了一种适合于MOS存储电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻微氮化的难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US6015997A

公开(公告)日：2000-01-18

申请号：US803174

申请日：1997-02-19

Applicant: Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P.S. Thakur ,  Scott DeBoer

Inventor： Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P.S. Thakur ,  Scott DeBoer

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/76 ,  H01L29/74 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L21/28044 ,  H01L21/28052 ,  H01L29/4941

Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

公开(公告)号：US6004869A

公开(公告)日：1999-12-21

申请号：US845616

申请日：1997-04-25

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205

CPC classification number: H01L21/76895 ,  H01L21/28061 ,  H01L21/32134 ,  H01L29/4941

Abstract: A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as cobalt, followed by a silicon layer and a top insulator layer. The blanket stack is patterned with resist to define the conductive lines. The stack is dry etched down to the near noble metal layer. The resist is then removed and the stack is annealed to react the near noble metal and silicon to form a conductive compound having fine grain size. The unreacted noble metal is then wet etched, using the conductive diffusion barrier as a wet etch stop. A further dry etch is then performed down to the substrate, using the top insulator layer as a mask. In this manner, only one mask is required to form the conductive line.