Semiconductor device and method for fabricating the same

    公开(公告)号:US06403991B1

    公开(公告)日:2002-06-11

    申请号:US09639754

    申请日:2000-08-15

    IPC分类号: H01L31072

    摘要: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically. Consequently, a ballast resistor that causes no variation in the resistance value can be connected to each of a plurality of the transistor elements.

    Semiconductor device
    46.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US07307298B2

    公开(公告)日:2007-12-11

    申请号:US10989388

    申请日:2004-11-17

    IPC分类号: H01L29/80 H01L31/12

    摘要: The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 17 is formed in an active region defined by an element separation portion 9 on a main surface of a substrate 1 comprising GaAs. The gate electrode 17 is patterned so as to extend in the vertical direction of the page surface between source electrodes 13 and drain electrodes 14, and to extend in left and right directions at other portions. Thus, the ratio of the gate electrode 17 disposed outside the active region is reduced, and the area of a gate pad 17A is reduced.

    摘要翻译: 本发明将用作射频模块中的开关元件的HEMT元件小型化。 单个栅极电极17形成在由包含GaAs的基板1的主表面上的元件分离部分9限定的有源区域中。 栅电极17被图案化以在源电极13和漏电极14之间的页表面的垂直方向上延伸,并且在其它部分沿左右方向延伸。 因此,设置在有源区域之外的栅电极17的比率减小,并且栅极焊盘17A的面积减小。

    Semiconductor device and manufacturing method of the same
    47.
    发明申请
    Semiconductor device and manufacturing method of the same 审中-公开
    半导体器件及其制造方法相同

    公开(公告)号:US20070134820A1

    公开(公告)日:2007-06-14

    申请号:US11702491

    申请日:2007-02-06

    申请人: Atsushi Kurokawa

    发明人: Atsushi Kurokawa

    IPC分类号: H01L21/00

    摘要: The present invention intends to provide a technique that can improve the capacitance density while securing the withstand voltage of a capacitor element. In order to achieve the above object, the present inventive manufacturing method of a semiconductor device includes forming a metal film on a silicon oxide film, forming a SiN film on the metal film, forming a metal film on the SiN film, etching the upper most metal film with a photoresist film as a mask to form an upper electrode, thereafter forming a silicon oxide film that covers the upper electrode, patterning by etching the silicon oxide film and the SiN film with a photoresist film as a mask to form a capacitor insulating film and sputter-etching the lowermost metal film with the patterned silicon oxide film as a mask to form a lower electrode.

    摘要翻译: 本发明旨在提供一种能够在确保电容器元件的耐受电压的同时提高电容密度的技术。 为了实现上述目的,本发明的半导体器件的制造方法包括在氧化硅膜上形成金属膜,在金属膜上形成SiN膜,在SiN膜上形成金属膜,蚀刻最多 金属膜以光致抗蚀剂膜为掩模形成上电极,然后形成覆盖上电极的氧化硅膜,通过用光致抗蚀剂膜蚀刻氧化硅膜和SiN膜作为掩模进行图案化,以形成绝缘的电容器 用图案化的氧化硅膜作为掩模对最下面的金属膜进行薄膜溅射蚀刻以形成下电极。

    Method for forming patterns on a semiconductor device using a lift off technique
    48.
    发明授权
    Method for forming patterns on a semiconductor device using a lift off technique 失效
    使用剥离技术在半导体器件上形成图案的方法

    公开(公告)号:US07214558B2

    公开(公告)日:2007-05-08

    申请号:US11257060

    申请日:2005-10-25

    IPC分类号: H01L21/00 H01L21/8235

    摘要: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

    摘要翻译: 提供了改进双极晶体管的性质的技术。 具体地说,通过剥离法在基台周围形成集电极时,在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜, 随后在衬底的整个表面上依次形成金锗(AuGe),镍(Ni)和Au,使得它们的堆叠膜不会变成隔离图案。 结果,基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接,有利于层叠膜在基台面4a上的剥离。 此外,通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻,或 n型InGaAs层。

    Semiconductor device, manufacturing method of the same and electronic device
    50.
    发明申请
    Semiconductor device, manufacturing method of the same and electronic device 审中-公开
    半导体器件及其制造方法及电子器件

    公开(公告)号:US20060138459A1

    公开(公告)日:2006-06-29

    申请号:US11316989

    申请日:2005-12-27

    IPC分类号: H01L31/109

    摘要: Provided is a semiconductor device equipped with HBTs capable of satisfying both thermal stability and reliability and having improved electrostatic breakdown voltage. The HBT according to the present invention is obtained by successively forming, over the main surface of a substrate made of a compound semiconductor, a sub-collector layer, a collector layer, a base layer, an emitter layer, a collector electrode electrically connected to the collector layer, a base electrode electrically connected to the base layer, an emitter mesa layer formed over the emitter layer and electrically connected to the emitter layer, and an emitter electrode electrically connected to the emitter mesa layer. The emitter mesa layer has a semiconductor layer made of an n type GaAs layer, a high concentration semiconductor layer made of an n+ type GaAs layer over the semiconductor layer and a ballast resistor layer made of an n type InGaAs layer over the high concentration semiconductor layer.

    摘要翻译: 提供了配备能够满足热稳定性和可靠性并具有改善的静电击穿电压的HBT的半导体器件。 根据本发明的HBT是通过在由化合物半导体制成的衬底的主表面上连续形成子集电极层,集电极层,基极层,发射极层,集电极,电连接到 集电极层,电连接到基极层的基极,在发射极层上形成并电连接到发射极层的发射极台面层和电连接到发射极台面层的发射极。 发射极台面层具有由n型GaAs层构成的半导体层,在半导体层上形成由n + +型GaAs层构成的高浓度半导体层和由n型GaAs层制成的镇流电阻层 InGaAs层在高浓度半导体层上。