公开(公告)号：US08476731B2

公开(公告)日：2013-07-02

申请号：US13349959

申请日：2012-01-13

申请人： Akihisa Terano ,  Kazuhiro Mochizuki ,  Takashi Ishigaki

发明人： Akihisa Terano ,  Kazuhiro Mochizuki ,  Takashi Ishigaki

IPC分类号： H01L29/47 ,  H01L29/40

CPC分类号： H01L29/872 ,  H01L29/0649 ,  H01L29/2003

摘要： In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.

摘要翻译： 在氮化物半导体上的肖特基电极形成区域中，肖特基电极和氮化物半导体层的表面的总长度比肖特基电极形成区域的周长长。 总长度优选比周长长10倍。 例如，肖特基电极同心圆形地形成。

公开(公告)号：US20060081879A1

公开(公告)日：2006-04-20

申请号：US11247234

申请日：2005-10-12

申请人： Kenichi Tanaka ,  Hidetoshi Matsumoto ,  Isao Ohbu ,  Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chisaki Takubo ,  Hiroyuki Uchiyama

发明人： Kenichi Tanaka ,  Hidetoshi Matsumoto ,  Isao Ohbu ,  Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chisaki Takubo ,  Hiroyuki Uchiyama

IPC分类号： H01L31/109

CPC分类号： H01L23/482 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.

摘要翻译： 本发明提供一种半导体器件，其包括有源部件，无源部件，布线和电极，并且在机械强度，小型化和热稳定性方面令人满意。 在半导体器件中，开口形成在活性部件的正下方。 这些开口填充有导体层。 还形成了未形成开口的导体层。

公开(公告)号：US06943387B2

公开(公告)日：2005-09-13

申请号：US10409455

申请日：2003-04-09

申请人： Isao Ohbu ,  Tomonori Tanoue ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa ,  Kazuhiro Mochizuki ,  Masami Ohnishi ,  Hidetoshi Matsumoto

发明人： Isao Ohbu ,  Tomonori Tanoue ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa ,  Kazuhiro Mochizuki ,  Masami Ohnishi ,  Hidetoshi Matsumoto

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/423 ,  H01L29/737 ,  H03F1/30 ,  H03F3/19 ,  H01L31/072

CPC分类号： H01L29/66318 ,  H01L29/0692 ,  H01L29/42304 ,  H01L29/7371 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H03F1/302 ,  H03F3/19 ,  H03F2203/21178

摘要： In a semiconductor device using an emitter top heterojunction bipolar transistor having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. This allows reduction of base/collector junction capacitance per unit emitter area, whereby a semiconductor device having high power adding efficiency and high power gain suitable for a power amplifier can be realized. Further, in a multistage power amplifier including first and second amplifier circuits each having one or more of bipolar transistors, a bipolar transistor in the first amplifier circuit uses an emitter having a planar shape in a rectangular shape, and a bipolar transistor in the second amplifier circuit uses an emitter having a ring-like shape and a base electrode only on the inner side of the emitter.

摘要翻译： 在使用具有环状形状的发射极顶面异质结双极晶体管的半导体器件中，提供了仅在环状发射极 - 基极结区域的内侧存在基极的结构。 这允许减小每单位发射极面积的基极/集电极结电容，由此可以实现具有高功率增加效率和适用于功率放大器的高功率增益的半导体器件。 此外，在包括具有一个或多个双极晶体管的第一和第二放大器电路的多级功率放大器中，第一放大器电路中的双极晶体管使用具有矩形形状的平面形状的发射极和第二放大器中的双极晶体管 电路仅在发射体的内侧使用具有环状形状的发射体和基极。

公开(公告)号：US06881639B2

公开(公告)日：2005-04-19

申请号：US10372774

申请日：2003-02-26

申请人： Kazuhiro Mochizuki ,  Kiyoshi Ouchi ,  Tomonori Tanoue

发明人： Kazuhiro Mochizuki ,  Kiyoshi Ouchi ,  Tomonori Tanoue

IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/737 ,  H03F1/30 ,  H03F3/19

CPC分类号： H01L21/263 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66318 ,  H01L29/7371 ,  H03F1/302 ,  H03F3/19

摘要： The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.

摘要翻译： 本发明提供一种半导体器件的制造方法，以低成本制造InGaAs基C顶HBT。 具有较小半径的氦离子注入未被不掺杂的InGaAs间隔层，n型InP集电极层，n型InGaAs覆盖层和集电体组成的叠层的p型InGaAs层（在外部基极区域中） 电极从垂直于外部基底层的表面的方向延伸，或者垂直于3度的角度。 因此，外部基极区域中的p型InGaAs保持p型导电和低电阻，并且外部发射极区域中的n型InAlAs层可以被制成高电阻性。 通过这种方法，可以以较低的成本在较小的芯片上制造InGaAs基C顶HBT，而不增加工艺数量。

公开(公告)号：US06696711B2

公开(公告)日：2004-02-24

申请号：US10120505

申请日：2002-04-12

申请人： Kazuhiro Mochizuki ,  Tohru Oka ,  Isao Ohbu ,  Kiichi Yamashita

发明人： Kazuhiro Mochizuki ,  Tohru Oka ,  Isao Ohbu ,  Kiichi Yamashita

IPC分类号： H01L310328

CPC分类号： H01L21/8252 ,  H01L27/0605 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30107 ,  H03F1/302 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device comprising a plurality of heterojunction bipolar transistors with their base layer made of GaAsSb or InGaAs, a GaAs substrate, and a buffer layer placed between the base layer and the substrate is fabricated. The substrate and the buffer layer that lie directly under the intrinsic regions of a part or all of the plurality of heterojunction bipolar transistors are removed. Thereby, a semiconductor device using HBTs that can operate with a power supply voltage of 2 V or below can be provided at reduced cost as a well-reliable product, and a power amplifier with high power conversion efficiency can be provided.

摘要翻译： 制造包括多个异质结双极晶体管的半导体器件，其基底层由GaAsSb或InGaAs制成，GaAs衬底以及位于基底层和衬底之间的缓冲层。 去除位于多个异质结双极晶体管的一部分或全部的本征区域正下方的衬底和缓冲层。 由此，作为可靠性良好的产品，可以以降低的成本提供能够以2V以下的电源电压工作的HBT的半导体装置，能够提供高功率转换效率的功率放大器。

公开(公告)号：US5668402A

公开(公告)日：1997-09-16

申请号：US66635

申请日：1993-05-24

申请人： Kazuhiro Mochizuki ,  Shigeo Goto ,  Chushirou Kusano ,  Masahiko Kawata ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Susumu Takahashi

发明人： Kazuhiro Mochizuki ,  Shigeo Goto ,  Chushirou Kusano ,  Masahiko Kawata ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Susumu Takahashi

IPC分类号： H01L29/73 ,  A61F7/02 ,  H01L21/20 ,  H01L21/331 ,  H01L21/338 ,  H01L29/04 ,  H01L29/205 ,  H01L29/737 ,  H01L29/812

CPC分类号： H01L29/045 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02609 ,  A61F2007/0265

摘要： A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

摘要翻译： 半导体器件包括由第一单晶半导体材料形成的半导体衬底和通过掺杂有易于表面分离的元件的第二单晶半导体材料形成在半导体衬底上的半导体层。 半导体衬底的表面由与第二单晶半导体材料的表面上形成的小平面基本相同的晶面形成，如果第二单晶半导体材料被外延生长，在第 100）平面的第一单晶半导体材料。

公开(公告)号：US20120223337A1

公开(公告)日：2012-09-06

申请号：US13349959

申请日：2012-01-13

申请人： Akihisa TERANO ,  Kazuhiro MOCHIZUKI ,  Takashi ISHIGAKI

发明人： Akihisa TERANO ,  Kazuhiro MOCHIZUKI ,  Takashi ISHIGAKI

IPC分类号： H01L29/16 ,  H01L29/20

CPC分类号： H01L29/872 ,  H01L29/0649 ,  H01L29/2003

摘要： In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.

摘要翻译： 在氮化物半导体上的肖特基电极形成区域中，肖特基电极和氮化物半导体层的表面的总长度比肖特基电极形成区域的周长长。 总长度优选比周长长10倍。 例如，肖特基电极同心圆形地形成。

公开(公告)号：US20070073448A1

公开(公告)日：2007-03-29

申请号：US11583885

申请日：2006-10-20

申请人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

发明人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

IPC分类号： G05D1/10

CPC分类号： H01L21/30617 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/66318 ,  H01L29/7371

摘要： A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.

摘要翻译： 一种半导体器件及其制造方法，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于截面形状的表面，以及其制造方法 。 存在于构成半导体器件的半导体衬底中的孔或台阶形成为正常台面形状，而与半导体衬底的表面上的晶体取向无关。 使用对蚀刻掩模下方的蚀刻速率比半导体衬底的深度方向的蚀刻速度更高的湿蚀刻溶液。

公开(公告)号：US20060163696A1

公开(公告)日：2006-07-27

申请号：US11208561

申请日：2005-08-23

申请人： Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

发明人： Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

IPC分类号： H01L27/082

CPC分类号： H01L29/7606 ,  H01L29/2003

摘要： The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation frequency of the transistor to several THZ, InN having a high electron saturation velocity or a material mainly composed of InN is used for a collector layer. In order to obtain characteristics with excellent reproducibility, it is useful to insert InGaN into an interface between the collector layer and the base layer. Using the metal base transistor of the present invention makes it possible to constitute an oscillator allowing a THz band oscillation. Further, the present invention provides a spectroscopic instrument applying this oscillator to at least one of a signal source and a local oscillator.

摘要翻译： 实现小型化，低成本的太赫兹频带光谱和荧光检测仪器最重要的任务是实现仪器中使用的振荡器的小型化和降低成本。 金属基极晶体管用于振荡器的有源元件。 为了将晶体管的最大振荡频率提高到几个THZ，具有高电子饱和速度的InN或主要由InN组成的材料用于集电极层。 为了获得具有优异再现性的特性，将InGaN插入到集电极层和基极层之间的界面是有用的。 使用本发明的金属基极晶体管可以构成允许THz频带振荡的振荡器。 此外，本发明提供了一种将该振荡器应用于信号源和本地振荡器中的至少一个的分光仪器。

公开(公告)号：US06743691B2

公开(公告)日：2004-06-01

申请号：US10026613

申请日：2001-12-27

申请人： Atsushi Kurokawa ,  Masao Yamane ,  Kazuhiro Mochizuki

发明人： Atsushi Kurokawa ,  Masao Yamane ,  Kazuhiro Mochizuki

IPC分类号： H01L218222

CPC分类号： H01L29/7304 ,  H01L21/8252 ,  H01L27/0605 ,  H01L28/20 ,  H01L29/73

摘要： A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically. Consequently, a ballast resistor that causes no variation in the resistance value can be connected to each of a plurality of the transistor elements.

摘要翻译： 通过并联连接多个晶体管元件来形成具有大电流容量的双极晶体管器件，每个晶体管元件具有分别形成在半导体衬底中的集电极层，基极层和发射极层。 在双极晶体管器件中，多个晶体管元件的基极层彼此平行地延伸，并且这些基极层彼此分离。 在每个分离的基底层中，第一基极形成在与发射极层的发射极结分离的基底层的一部分上，并且第二基极形成在基极层的更靠近发射极结的另一部分 比第一基极。 为了将多个晶体管元件的基极电极彼此平行地配置，基极配线与这些元件的第一基极电连接。 因此，不会导致电阻值变动的镇流电阻器可以连接到多个晶体管元件中的每一个。