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公开(公告)号：US4890261A
公开(公告)日：1989-12-26
申请号：US206417
申请日：1988-06-14
IPC分类号： G11C7/00 , G06F12/04 , G11C7/10 , G11C8/12 , G11C11/401
CPC分类号： G11C8/12 , G11C7/1006
摘要： A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.
摘要翻译： 半导体存储器的字长可变电路包括与存储单元阵列的行或列对应地设置的移位寄存器。 移位寄存器的第一级的输入连接到最后级的输出端，移位寄存器的区域被分组以形成固定的再循环路径。 可以通过修改移位寄存器中存储的数据而不改变其再循环路径来改变字长。
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公开(公告)号：US4887136A
公开(公告)日：1989-12-12
申请号：US110462
申请日：1987-10-20
申请人： Yoshio Matsuda , Kazuyasu Fujishima
发明人： Yoshio Matsuda , Kazuyasu Fujishima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829 , Y10S257/911
摘要： A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.
摘要翻译： 一种动态半导体存储器件，包括具有一个沟槽的衬底，该沟槽包括用于存储器单元电容两位的两个电容器，以及用于读取，写入和存储由电荷表示的信息的晶体管的两个元件，其对称地布置在沟槽的中心部分处 对应于两位的存储单元，以及形成在底部和侧壁上的沟槽中心的场氧化膜，用于分离电容器和元件。
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43.发明授权Semiconductor memory device having improved resistance to alpha particle induced soft errors 失效半导体存储器件具有改善的对α粒子诱导的软错误的抵抗力
公开(公告)号：US4833645A
公开(公告)日：1989-05-23
申请号：US929367
申请日：1986-11-12
申请人： Yoshio Matsuda , Kazuyasu Fujishima
发明人： Yoshio Matsuda , Kazuyasu Fujishima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10805
摘要： In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.
摘要翻译： 在本发明的半导体存储装置中，在p型半导体基板（1）上形成与位线（12）连接的漏型扩散区域（9a），形成型源扩散区域（9b） 与n型漏极区域（9a）具有规定的间隔。 在p型硅基板（1）上，以高杂质密度的p型扩散区域（16a）和高杂质浓度的p型扩散区域（16b）以与n型漏极扩散接触的方式形成 区域（9a）和n型源极扩散区域（9b），但不在n沟道MOS晶体管（18）的沟道区域中。 因此，可以在不改变传输门晶体管的阈值电压的情况下降低α粒子产生的电荷。
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公开(公告)号：US5550769A
公开(公告)日：1996-08-27
申请号：US336114
申请日：1994-11-04
摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.
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45.发明授权Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
公开(公告)号：US5509132A
公开(公告)日：1996-04-16
申请号：US283487
申请日：1994-08-01
IPC分类号： G06F12/08 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/41
CPC分类号： G06F12/0893 , G11C7/1051
摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
摘要翻译： 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。
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公开(公告)号：US5416734A
公开(公告)日：1995-05-16
申请号：US28917
申请日：1993-03-08
摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.
摘要翻译： 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。
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47.发明授权Semiconductor memory device with a built-in cache memory and operating method thereof 失效具有内置缓存存储器的半导体存储器件及其操作方法
公开(公告)号：US5226139A
公开(公告)日：1993-07-06
申请号：US637872
申请日：1991-01-08
IPC分类号： G06F9/38 , G06F12/08 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/41
CPC分类号： G06F9/3824 , G06F12/0893 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
摘要翻译： 具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。 存储单元阵列（1）被分成多个块（B1〜B16）。 每个块被分成多个子块，每个子块具有多个列。 在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。 响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。 同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。 因此，存储在寄存器（16a）中的数据被高速读出
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公开(公告)号：US5222047A
公开(公告)日：1993-06-22
申请号：US566809
申请日：1990-08-13
CPC分类号： G11C8/14 , G11C7/1036 , G11C7/1039 , G11C8/18 , H01L2924/01074
摘要： In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.
摘要翻译： 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。
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49.发明授权Semiconductor memory device containing a cache and an operation method thereof 失效包含高速缓存的半导体存储器件及其操作方法
公开(公告)号：US5179687A
公开(公告)日：1993-01-12
申请号：US542682
申请日：1990-06-25
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0893 , G11C11/4096
摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.
摘要翻译： 用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器 用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。 缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。 在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。
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50.发明授权Bit line structure for semiconductor memory device with bank separation at cross-over regions 失效半导体存储器件的位线结构，在交叉区域具有银行分离
公开(公告)号：US5461589A
公开(公告)日：1995-10-24
申请号：US145733
申请日：1993-11-04
摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.
摘要翻译： 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。
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