-
1.发明授权Semiconductor memory device with cache memory addressable by block within each column 失效具有高速缓存存储器的半导体存储器件可在每列内通过块寻址
公开(公告)号：US4926385A
公开(公告)日：1990-05-15
申请号：US228589
申请日：1988-08-05
IPC分类号： G11C11/401 , G06F12/08 , G11C7/10 , G11C8/12 , G11C11/41
CPC分类号： G11C7/103 , G06F12/0893 , G11C8/12
摘要： A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.
摘要翻译： 半导体存储器包括具有多个位线的存储单元阵列和与位线相交的多个字线。 多个存储单元分别布置在位线和字线的交点处。 字线选择电路响应于行地址选择一个字线，并读出存储在与所选字线相关联的存储单元中的每一个位线信息。 多个读出放大器与存储器的相应行相关联，用于检测和放大存储在相应存储单元中的信息。 当应用列地址时，第一列选择器电路选择对应于列地址的读出放大器，并读取保持在读出放大器中的信息。 通过将存储单元阵列划分成位线组来形成块，每个组包括预定数量的位线，其中块信息同时从对应于所选块的位线的位线的相应位组传送 应用所选的块。 数据寄存器保存相关块的信息。 当应用列地址时，第二列选择器从数据寄存器读取与列地址对应的数据。
-
2.发明授权Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
公开(公告)号：US5509132A
公开(公告)日：1996-04-16
申请号：US283487
申请日：1994-08-01
IPC分类号： G06F12/08 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/41
CPC分类号： G06F12/0893 , G11C7/1051
摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
摘要翻译： 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。
-
3.发明授权Semiconductor memory device with a built-in cache memory and operating method thereof 失效具有内置缓存存储器的半导体存储器件及其操作方法
公开(公告)号：US5226139A
公开(公告)日：1993-07-06
申请号：US637872
申请日：1991-01-08
IPC分类号： G06F9/38 , G06F12/08 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/41
CPC分类号： G06F9/3824 , G06F12/0893 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
摘要翻译： 具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。 存储单元阵列（1）被分成多个块（B1〜B16）。 每个块被分成多个子块，每个子块具有多个列。 在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。 响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。 同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。 因此，存储在寄存器（16a）中的数据被高速读出
-
4.发明授权Semiconductor memory device containing a cache and an operation method thereof 失效包含高速缓存的半导体存储器件及其操作方法
公开(公告)号：US5179687A
公开(公告)日：1993-01-12
申请号：US542682
申请日：1990-06-25
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0893 , G11C11/4096
摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.
摘要翻译： 用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器 用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。 缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。 在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。
-
公开(公告)号：US5371714A
公开(公告)日：1994-12-06
申请号：US26225
申请日：1993-02-26
CPC分类号： G11C8/14 , G11C7/1036 , G11C7/1039 , G11C8/18 , H01L2924/01074
摘要： In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.
摘要翻译： 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。
-
公开(公告)号：US5103426A
公开(公告)日：1992-04-07
申请号：US528511
申请日：1990-05-25
IPC分类号： H01L21/82 , G11C5/06 , G11C8/00 , G11C8/12 , G11C11/401 , G11C29/00 , H01L21/822 , H01L27/04 , H01L27/10 , H03M7/00 , H03M7/22
CPC分类号： G11C8/12 , G11C5/066 , G11C29/006
摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.
-
7.发明授权Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers 失效包括交叉点和多个互连层的半导体存储器件的位线结构
公开(公告)号：US5214601A
公开(公告)日：1993-05-25
申请号：US876690
申请日：1992-04-28
摘要： A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N (N being an integer), although advantages of the invention may be obtained with division of the bit lines into 3N, and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. In a preferred embodiment, the cross parts are provided in regions for forming restore circuits or sense amplifiers. In a further embodiment, a dummy word line for selecting dummy cells for providing a reference potential is selected according to the position of a selected word line.
摘要翻译： 折叠位线结构的半导体存储器件包括每个位线对的至少一部分中的交叉部分，使得与相邻位线对的耦合电容值相对于成对的位线彼此相等。 优选地，各位线对被均等地划分为4N（N是整数），尽管可以通过将位线划分为3N来获得本发明的优点，并且在分割点处提供交叉部分，使得位线对 将相同分割点处的交叉部分布置在交替的位线对上。 在优选实施例中，交叉部分设置在用于形成恢复电路或感测放大器的区域中。 在另一实施例中，根据所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。
-
公开(公告)号：US4972380A
公开(公告)日：1990-11-20
申请号：US206416
申请日：1988-06-14
IPC分类号： H01L21/82 , G11C5/06 , G11C8/00 , G11C8/12 , G11C11/401 , G11C29/00 , H01L21/822 , H01L27/04 , H01L27/10 , H03M7/00 , H03M7/22
CPC分类号： G11C8/12 , G11C5/066 , G11C29/006
摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.
摘要翻译： 用于功能块的地址解码电路包括彼此串行连接的分支部分，其中当选择信号被施加到第一个时，根据地址信号的第一位信息在两个输出部分之一上输出选择信号 阶段分支部分。 根据选择信号，施加选择信号的第二级输出部分响应于地址信号的第二位信息，在两个输出部分之一上输出选择信号。 此后，根据从前一级施加的选择信号，第三至最后级的每个分支部分响应于第三位的相应内容输出地址信号的最后一位的两个输出部分之一上的选择信号。 通过该选择信号，选择作为功能块部分的存储单元并被激活。
-
公开(公告)号：US4890261A
公开(公告)日：1989-12-26
申请号：US206417
申请日：1988-06-14
IPC分类号： G11C7/00 , G06F12/04 , G11C7/10 , G11C8/12 , G11C11/401
CPC分类号： G11C8/12 , G11C7/1006
摘要： A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.
摘要翻译： 半导体存储器的字长可变电路包括与存储单元阵列的行或列对应地设置的移位寄存器。 移位寄存器的第一级的输入连接到最后级的输出端，移位寄存器的区域被分组以形成固定的再循环路径。 可以通过修改移位寄存器中存储的数据而不改变其再循环路径来改变字长。
-
公开(公告)号：US5588130A
公开(公告)日：1996-12-24
申请号：US283367
申请日：1994-08-01
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
-
-
-
-
-
-
-
-
-
搜索结果
142 条记录 (耗时 0.022 秒)
