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    Semiconductor memory device with cache memory addressable by block within each column
    1.
    发明授权
    Semiconductor memory device with cache memory addressable by block within each column 失效
    具有高速缓存存储器的半导体存储器件可在每列内通过块寻址

    公开(公告)号：US4926385A

    公开(公告)日：1990-05-15

    申请号：US228589

    申请日：1988-08-05

    申请人： Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    发明人： Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    IPC分类号： G11C11/401 ,  G06F12/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/41

    CPC分类号： G11C7/103 ,  G06F12/0893 ,  G11C8/12

    摘要： A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.

    摘要翻译： 半导体存储器包括具有多个位线的存储单元阵列和与位线相交的多个字线。 多个存储单元分别布置在位线和字线的交点处。 字线选择电路响应于行地址选择一个字线，并读出存储在与所选字线相关联的存储单元中的每一个位线信息。 多个读出放大器与存储器的相应行相关联，用于检测和放大存储在相应存储单元中的信息。 当应用列地址时，第一列选择器电路选择对应于列地址的读出放大器，并读取保持在读出放大器中的信息。 通过将存储单元阵列划分成位线组来形成块，每个组包括预定数量的位线，其中块信息同时从对应于所选块的位线的位线的相应位组传送 应用所选的块。 数据寄存器保存相关块的信息。 当应用列地址时，第二列选择器从数据寄存器读取与列地址对应的数据。

    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof
    2.
    发明授权
    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效
    具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法

    公开(公告)号：US5509132A

    公开(公告)日：1996-04-16

    申请号：US283487

    申请日：1994-08-01

    申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/41

    CPC分类号： G06F12/0893 ,  G11C7/1051

    摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.

    摘要翻译： 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。

    Semiconductor memory device with a built-in cache memory and operating method thereof
    3.
    发明授权
    Semiconductor memory device with a built-in cache memory and operating method thereof 失效
    具有内置缓存存储器的半导体存储器件及其操作方法

    公开(公告)号：US5226139A

    公开(公告)日：1993-07-06

    申请号：US637872

    申请日：1991-01-08

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Hideto Hidaka ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Hideto Hidaka ,  Mikio Asakura

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/41

    CPC分类号： G06F9/3824 ,  G06F12/0893 ,  G11C11/408 ,  G11C11/4096

    摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed

    摘要翻译： 具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。 存储单元阵列（1）被分成多个块（B1〜B16）。 每个块被分成多个子块，每个子块具有多个列。 在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。 响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。 同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。 因此，存储在寄存器（16a）中的数据被高速读出

    Semiconductor memory device containing a cache and an operation method thereof
    4.
    发明授权
    Semiconductor memory device containing a cache and an operation method thereof 失效
    包含高速缓存的半导体存储器件及其操作方法

    公开(公告)号：US5179687A

    公开(公告)日：1993-01-12

    申请号：US542682

    申请日：1990-06-25

    申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G06F12/08 ,  G11C11/4096

    CPC分类号： G06F12/0893 ,  G11C11/4096

    摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.

    摘要翻译： 用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器 用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。 缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。 在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。