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公开(公告)号：US20050151168A1
公开(公告)日：2005-07-14
申请号：US11022773
申请日：2004-12-28
IPC分类号： H01L21/8234 , G11C16/04 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/73 , H01L21/82
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
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42.发明授权公开(公告)号：US07585726B2
公开(公告)日：2009-09-08
申请号：US11350118
申请日：2006-02-09
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material. Therefore, it is unnecessary to perform the batch forming of the control gate material, the interpoly dielectric film material, and the floating gate material in the case of processing the control gates, thereby ensuring adequate interpoly dielectric film capacitance.
摘要翻译： 本发明能够避免非易失性半导体存储器件中的耦合比的降低。 由于控制栅极材料，间隔电介质膜材料和浮栅材料的分批形成的困难而引起的还原是耦合比，伴随着字线宽度的减小。 此外，本发明能够避免在栅极氧化膜上的批次形成中引起的损坏。 在形成非易失性存储器的存储单元的浮动栅极之前，为存储单元的每个浮置栅极形成由绝缘层包围的空间，使得浮动栅极被埋在空间中。 通过在浮置栅极材料沉积之后以自对准方式处理浮置栅极来实现该结构。 因此，在处理控制栅极的情况下，不需要执行控制栅极材料，多晶硅介电膜材料和浮置栅极材料的批量形成，从而确保足够的多层介电膜电容。
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43.发明申请公开(公告)号：US20050212034A1
公开(公告)日：2005-09-29
申请号：US11031484
申请日：2005-01-10
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/8239 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42328
摘要： A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 3 of a memory cell with an inverse T-shape and the dimension of a part of the floating gate through the control gate 4 and the second insulator film 8 being smaller than the bottom part of the floating gate, the effects of a threshold voltage shift is reduced maintaining the adequate area of the gap between the floating gate 3 and the control gate 4, decreasing the opposing area of the gap of the floating gates 3 underneath the adjoining word lines WL, maintaining the capacity coupling ratio between the floating gate 3 and the control gate, and reducing the opposing area of the gap of the adjoining floating gates 3.
摘要翻译： 一种实现相邻浮栅之间的电容减小的技术和由非易失性半导体存储器件中相邻的存储单元之间的干扰引起的阈值电压偏移与90nm代之后的周期内的小型化的进步。 通过使具有逆T形的存储单元的浮置栅极3和通过控制栅极4和第二绝缘膜8的一部分浮动栅极的尺寸小于浮动栅极的底部的尺寸， 维持阈值电压偏移的维持维持浮动栅极3和控制栅极4之间的间隙的适当面积，减小相邻字线WL下面的浮动栅极3的间隙的相对面积，从而保持 浮动栅极3和控制栅极，并且减小邻接的浮动栅极3的间隙的相对面积。
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公开(公告)号：US06849502B2
公开(公告)日：2005-02-01
申请号：US10457656
申请日：2003-06-10
IPC分类号： H01L21/8234 , G11C16/04 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
摘要翻译： 具有包括第一至第三栅电极的非易失性存储器的半导体器件的可靠性得到增强。 利用具有第一栅电极（浮栅电极），第二栅电极（控制栅电极）和第三栅电极的闪速存储器，隔离部分以自对准的方式形成，以抵抗用于形成第三栅电极的导体膜的图案 填充相应的隔离沟槽，并且在形成隔离部件之前形成用于在外围电路区域中选择的nMIS的栅极绝缘膜。 通过这样做，可以减少由隔离部分发生的应力引起的用于选择性nMIS的栅极绝缘膜的缺陷。 此外，通过包括堆叠的存储单元的情况的半导体器件，可以形成用作形成隔离部件的自对准方式的掩模的用于形成第三栅电极的导体膜的图案，而不对准通道 。
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公开(公告)号：US07471563B2
公开(公告)日：2008-12-30
申请号：US11652023
申请日：2007-01-11
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。
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公开(公告)号：US07023048B2
公开(公告)日：2006-04-04
申请号：US10417269
申请日：2003-04-17
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material. Therefore, it is unnecessary to perform the batch forming of the control gate material, the interpoly dielectric film material, and the floating gate material in the case of processing the control gates, thereby ensuring adequate interpoly dielectric film capacitance.
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47.发明申请公开(公告)号：US20060022259A1
公开(公告)日：2006-02-02
申请号：US11239338
申请日：2005-09-30
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11546 , H01L29/42324
摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.
摘要翻译： 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。
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公开(公告)号：US06927443B2
公开(公告)日：2005-08-09
申请号：US10682479
申请日：2003-10-10
IPC分类号： H01L21/8247 , G11C8/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792 , H01L25/108
CPC分类号： G11C16/0408 , H01L27/115
摘要： A nonvolatile semiconductor memory device improved with integration degree, in which the gate of the selection transistors is separated on each of active regions, first and second selection transistors are arranged in two stages in the direction of the global bit line, the gates for the selection transistors in each stage are disposed on every other active regions, contact holes are formed in mirror asymmetry with respect to line B—B in the connection portion for the active regions, the gate is connected through the contact hole to the wiring, the adjacent active regions are connected entirely in one selection transistor portion and connected in an H-shape for adjacent two active regions in another selection transistor portion, and the contact hole is formed in the connection portion and connected when the global bit line, whereby the pitch for the selection transistor portion can be decreased in the direction of the global bit line.
摘要翻译： 一种以积分度改善的非易失性半导体存储器件，其中选择晶体管的栅极在每个有源区域上分离，第一和第二选择晶体管沿全局位线的方向分两级布置，用于选择栅极 每个级中的晶体管设置在每个其他有源区上，在有源区的连接部分中，相对于线BB在接触孔中形成接触孔，栅极通过接触孔连接到布线，相邻的有源区是 完全在一个选择晶体管部分连接并连接在另一个选择晶体管部分中的相邻两个有源区域的H形中，并且接触孔形成在连接部分中，并且当全局位线连接时，由此选择晶体管的间距 部分可以在全局位线的方向上减小。
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公开(公告)号：US06670671B2
公开(公告)日：2003-12-30
申请号：US10166145
申请日：2002-06-11
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions is performed to form the diffusion layers and heavily impurity doped region of the same conductivity type as the well in a self-alignment manner relative to the gate.
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50.发明授权公开(公告)号：US07195967B2
公开(公告)日：2007-03-27
申请号：US10701497
申请日：2003-11-06
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions is performed to form the diffusion layers and heavily impurity doped region of the same conductivity type as the well in a self-alignment manner relative to the gate.
摘要翻译： 在源极/漏极扩散层之间的沟道区域中，与扩散区域分开的区域掺杂与阱相同导电类型的杂质。 通过使用预先形成的栅极，执行相反方向的倾斜离子注入，以相对于栅极以自对准方式形成与阱相同导电类型的扩散层和重杂质掺杂区。
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