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    Nonvolatile semiconductor memory device and manufacturing method thereof
    2.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20060022259A1

    公开(公告)日：2006-02-02

    申请号：US11239338

    申请日：2005-09-30

    申请人： Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

    发明人： Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42324

    摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.

    摘要翻译： 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07471563B2

    公开(公告)日：2008-12-30

    申请号：US11652023

    申请日：2007-01-11

    申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    IPC分类号： G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

    摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

    摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06927443B2

    公开(公告)日：2005-08-09

    申请号：US10682479

    申请日：2003-10-10

    申请人： Tsuyoshi Arigane ,  Takashi Kobayashi ,  Yoshitaka Sasago

    发明人： Tsuyoshi Arigane ,  Takashi Kobayashi ,  Yoshitaka Sasago

    IPC分类号： H01L21/8247 ,  G11C8/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L25/108

    CPC分类号： G11C16/0408 ,  H01L27/115

    摘要： A nonvolatile semiconductor memory device improved with integration degree, in which the gate of the selection transistors is separated on each of active regions, first and second selection transistors are arranged in two stages in the direction of the global bit line, the gates for the selection transistors in each stage are disposed on every other active regions, contact holes are formed in mirror asymmetry with respect to line B—B in the connection portion for the active regions, the gate is connected through the contact hole to the wiring, the adjacent active regions are connected entirely in one selection transistor portion and connected in an H-shape for adjacent two active regions in another selection transistor portion, and the contact hole is formed in the connection portion and connected when the global bit line, whereby the pitch for the selection transistor portion can be decreased in the direction of the global bit line.

    摘要翻译： 一种以积分度改善的非易失性半导体存储器件，其中选择晶体管的栅极在每个有源区域上分离，第一和第二选择晶体管沿全局位线的方向分两级布置，用于选择栅极 每个级中的晶体管设置在每个其他有源区上，在有源区的连接部分中，相对于线BB在接触孔中形成接触孔，栅极通过接触孔连接到布线，相邻的有源区是 完全在一个选择晶体管部分连接并连接在另一个选择晶体管部分中的相邻两个有源区域的H形中，并且接触孔形成在连接部分中，并且当全局位线连接时，由此选择晶体管的间距 部分可以在全局位线的方向上减小。

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20070109870A1

    公开(公告)日：2007-05-17

    申请号：US11652023

    申请日：2007-01-11

    申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

    摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

    摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

    Non-volatile semiconductor storage device and the manufacturing method thereof
    7.
    发明申请
    Non-volatile semiconductor storage device and the manufacturing method thereof 审中-公开
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US20060183284A1

    公开(公告)日：2006-08-17

    申请号：US11316817

    申请日：2005-12-27

    申请人： Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Tetsufumi Kawamura ,  Hitoshi Kume ,  Takashi Kobayashi

    发明人： Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Tetsufumi Kawamura ,  Hitoshi Kume ,  Takashi Kobayashi

    IPC分类号： H01L21/336

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/40114

    摘要： High integration and making a non-volatile semiconductor memory efficient have been promoted. The memory cell consists of a floating gate, a control gate constituting a word line WL and a MOS transistor having an assist gate. The thickness of the gate oxide film of the assist gate is thinner than the thickness of the gate oxide layer of the floating gate, and the dimensions of the assist gate (gate width) in the direction lying along the word line WL is smaller than the gate length of the floating gate in the direction lying along the word line WL. Moreover, the channel dopant concentration underneath the assist gate is lower than the channel dopant concentration underneath the floating gate.

    摘要翻译： 高集成度和非易失性半导体存储器的高效率得到了提升。 存储单元包括浮置栅极，构成字线WL的控制栅极和具有辅助栅极的MOS晶体管。 辅助栅极的栅极氧化膜的厚度比浮栅的栅极氧化物层的厚度薄，并且沿着字线WL的方向上的辅助栅极（栅极宽度）的尺寸小于 浮栅的沿着字线WL的方向的栅极长度。 此外，辅助栅极下方的沟道掺杂剂浓度低于浮栅下方的沟道掺杂剂浓度。

    Semiconductor memory device
    8.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060039195A1

    公开(公告)日：2006-02-23

    申请号：US11197485

    申请日：2005-08-05

    申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

    摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

    摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

    Nonvolatile semiconductor memory device
    9.
    发明申请
    Nonvolatile semiconductor memory device 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20050195630A1

    公开(公告)日：2005-09-08

    申请号：US11060422

    申请日：2005-02-18

    申请人： Tsuyoshi Arigane ,  Takashi Kobayashi ,  Yoshitaka Sasaga

    发明人： Tsuyoshi Arigane ,  Takashi Kobayashi ,  Yoshitaka Sasaga

    IPC分类号： H01L21/8247 ,  B41J29/38 ,  G11C7/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11524

    摘要： A nonvolatile semiconductor memory device to be manufactured at a high production yield has memory cells disposed in a highly integrated manner by suppressing the occurrence of dislocation typically caused by such highly integrated disposition of the memory cells. In order to achieve is result, each field shielding transistor is formed in a select transistor region having a small isolation width, and 0 V is applied to a gate of the field shielding transistor to isolate each local bit line from the others. The gate of each field shielding transistor is connected to another one with a gate member, so that the layout area is reduced more than when a contact hole is provided directly at the gate of each field shielding transistor.

    摘要翻译： 以高生产率制造的非易失性半导体存储器件通过抑制通常由这种高度集成化的存储单元布置而引起的位错的发生，以高度集成的方式设置存储单元。 为了获得结果，每个场屏蔽晶体管形成在具有小隔离宽度的选择晶体管区域中，并且0V施加到场屏蔽晶体管的栅极以将每个局部位线与其它位线隔离。 每个场屏蔽晶体管的栅极与具有栅极部件的另一个栅极连接，使得布局面积比在每个场屏蔽晶体管的栅极处直接提供接触孔时更小。