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公开(公告)号：US20130228739A1
公开(公告)日：2013-09-05
申请号：US13884263
申请日：2010-12-06
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
摘要翻译： 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时，包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻， 并且防止形成在层叠膜上的位线上升。 作为其手段，电连接到沟道半导体层的导电层设置在堆叠膜的正上方。
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2.发明授权Miniaturized virtual grounding nonvolatile semiconductor memory device and manufacturing method thereof 有权小型虚拟接地非易失性半导体存储器件及其制造方法公开(公告)号：US07411242B2
公开(公告)日：2008-08-12
申请号：US11239338
申请日：2005-09-30
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11546 , H01L29/42324
摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.
摘要翻译： 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。
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公开(公告)号：US20070109870A1
公开(公告)日：2007-05-17
申请号：US11652023
申请日：2007-01-11
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。
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公开(公告)号：US07190017B2
公开(公告)日：2007-03-13
申请号：US11022773
申请日：2004-12-28
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
摘要翻译： 具有包括第一至第三栅电极的非易失性存储器的半导体器件的可靠性得到增强。 利用具有第一栅电极（浮栅电极），第二栅电极（控制栅电极）和第三栅电极的闪速存储器，隔离部分以自对准的方式形成，以抵抗用于形成第三栅电极的导体膜的图案 填充相应的隔离沟槽，并且在形成隔离部件之前形成用于在外围电路区域中选择的nMIS的栅极绝缘膜。 通过这样做，可以减少由隔离部分发生的应力引起的用于选择性nMIS的栅极绝缘膜的缺陷。 此外，通过包括堆叠的存储单元的情况的半导体器件，可以形成用作形成隔离部件的自对准方式的掩模的用于形成第三栅电极的导体膜的图案，而不对准通道 。
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公开(公告)号：US07184318B2
公开(公告)日：2007-02-27
申请号：US11197485
申请日：2005-08-05
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
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6.发明申请公开(公告)号：US20060001081A1
公开(公告)日：2006-01-05
申请号：US11166114
申请日：2005-06-27
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0491 , H01L27/11521
摘要： A leakage current flowing between data lines of a nonvolatile semiconductor memory is reduced. In a memory array of a nonvolatile semiconductor memory device having an AND type flash memory, a concave portion is formed in a junction isolation area between adjacent word limes and between adjacent assist gate wirings AGL, and the height of a main surface (first main surface) of a semiconductor substrate in the region where the concave portion is formed is made lower than that of the main surface (second main surface) of the semiconductor substrate to which an assist gate wiring is facing. As a result, it is possible to control the leakage current that flows between the drain line and source line in the aforementioned junction isolation region during operation of a flash memory.
摘要翻译： 在非易失性半导体存储器的数据线之间流动的漏电流减少。 在具有AND型闪速存储器的非易失性半导体存储器件的存储器阵列中，在相邻字灰度之间和相邻辅助栅极布线AGL之间的结隔离区域中形成凹部，并且在主表面（第一主表面 ）形成在形成有凹部的区域中的半导体衬底的低于辅助栅极布线所面对的半导体衬底的主表面（第二主表面）的厚度。 结果，可以在闪速存储器的操作期间控制在上述结隔离区域中的漏极线和源极线之间流动的漏电流。
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公开(公告)号：US20050151168A1
公开(公告)日：2005-07-14
申请号：US11022773
申请日：2004-12-28
IPC分类号： H01L21/8234 , G11C16/04 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/73 , H01L21/82
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
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公开(公告)号：US08866123B2
公开(公告)日：2014-10-21
申请号：US13884331
申请日：2010-11-22
IPC分类号： H01L47/00 , H01L45/00 , H01L29/792 , H01L27/24 , H01L29/66 , H01L27/115
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
摘要翻译： 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 双层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。
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公开(公告)号：US08772746B2
公开(公告)日：2014-07-08
申请号：US13349653
申请日：2012-01-13
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2454 , H01L27/2472 , H01L45/144 , H01L45/1675
摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.
摘要翻译： 可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。 在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和 电阻变化元件的一部分设置在多条字线的上方。 这样的配置可以减小单元面积并确保设计自由度。
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公开(公告)号：US08642988B2
公开(公告)日：2014-02-04
申请号：US13588112
申请日：2012-08-17
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , G11C13/0004 , G11C2213/71 , G11C2213/74 , G11C2213/75 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06
摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.
摘要翻译： 非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且 粘合层的电阻相对于沟道层的延伸方向高。
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