公开(公告)号：US06731601B1

公开(公告)日：2004-05-04

申请号：US09477723

申请日：2000-01-05

Applicant: Gopal Krishna ,  Ching Yu ,  Peter Chow ,  Jenny Liu Fischer ,  Bahadir Erimli

Inventor： Gopal Krishna ,  Ching Yu ,  Peter Chow ,  Jenny Liu Fischer ,  Bahadir Erimli

IPC: G01R3108

CPC classification number: H04L47/26 ,  H04L12/413 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/50 ,  H04L49/506

Abstract: A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter within any one of the respective switch ports if backpressure is asserted by that port. The resetting of the retry counter within a port after assertion of backpressure affords the port a greater probability of winning collision mediation under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch.

Abstract translation: 网络交换机具有用于根据CSMA / CD协议与数据分组与各个计算机网络节点进行通信的交换机端口，如果该端口反向压力，那么在相应交换机端口内的任何一个中重置重试计数器。 在启用背压后，端口内的重试计数器的复位为CSMA / CD协议提供了获胜冲突中介的更大概率，从而更快地减轻了网络交换机中可能发生的拥塞。

公开(公告)号：US06721277B1

公开(公告)日：2004-04-13

申请号：US09321086

申请日：1999-05-28

Applicant: Ching Yu ,  Jeffrey Dwork ,  John Chiang

Inventor： Ching Yu ,  Jeffrey Dwork ,  John Chiang

IPC: G01R3108

CPC classification number: G06F1/12 ,  H04L7/02

Abstract: A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.

Abstract translation: 提供外部主机处理器访问位于不同时钟域中的寄存器的新颖方法。 该方法包括将主机处理器接口信号转换成内部寄存器接口信号，并通过内部寄存器接口与寄存器执行握手的步骤。 握手包括向寄存器提供寄存器访问信号以使得能够访问所选择的寄存器，并且响应于寄存器访问信号产生寄存器就绪信号。 相对于寄存器就绪信号延迟的同步信号可以用于与处理器接口同步位于不同时钟域的寄存器。

公开(公告)号：US06625146B1

公开(公告)日：2003-09-23

申请号：US09321833

申请日：1999-05-28

Applicant: Shashank Merchant ,  Robert A. Williams ,  Ching Yu

Inventor： Shashank Merchant ,  Robert A. Williams ,  Ching Yu

IPC: H04L1256

CPC classification number: H04L49/901 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/90

Abstract: A method and apparatus are disclosed for operating a network switch without the use of a CPU. A control interface is used to connect the network switch to the external CPU. The control interface generates an initialization signal indicative of the absence of a CPU. Upon receiving the initialization signal, an internal rules checker initializes the network switch. The internal rules checker will then begin receiving data frames and forwarding them to the appropriate network stations based on a source address and destination address contained in the data frames.

Abstract translation: 公开了一种用于在不使用CPU的情况下操作网络交换机的方法和装置。 控制接口用于将网络交换机连接到外部CPU。 控制接口产生指示不存在CPU的初始化信号。 一旦接收到初始化信号，内部规则检查器初始化网络交换机。 然后，内部规则检查器将基于数据帧中包含的源地址和目的地地址开始接收数据帧并将其转发到相应的网络站。

公开(公告)号：US06442137B1

公开(公告)日：2002-08-27

申请号：US09317143

申请日：1999-05-24

Applicant: Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli ,  John M. Chiang ,  Shashank Merchant ,  Robert Williams ,  Edward Yang ,  Chandan Egbert ,  Vallath Nandakumar ,  Ian Lam ,  Eric Tsin-Ho Leung

Inventor： Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli ,  John M. Chiang ,  Shashank Merchant ,  Robert Williams ,  Edward Yang ,  Chandan Egbert ,  Vallath Nandakumar ,  Ian Lam ,  Eric Tsin-Ho Leung

IPC: H04L522

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/352 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9078

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.

Abstract translation: 网络交换机具有用于根据以太网（IEEE 802.3）协议的具有各网络节点的数据分组全双工通信的交换机端口，该协议基于网络流量的比较量在高数据速率端口之间分配规定数量的外部存储器带宽时隙 各个端口。 外部存储器接口中的调度器根据规定的顺序，初始地将存储器访问时隙分配给相应的高数据速率端口。 如果调度器随后检测到具有较少时隙的端口上的网络数据流量高于具有更多时隙的端口上的流量，则这些时隙在高数据速率端口之间交换。 此外，高数据速率端口之一中的时钟多路复用器根据分配给该端口的时隙数来调整端口的数据速率。 在高数据速率端口之间交换带宽时隙以及端口时钟速率的调整使得能够有效地使用有限的存储器带宽资源。

公开(公告)号：US06389557B1

公开(公告)日：2002-05-14

申请号：US09154077

申请日：1998-09-16

Applicant: Ching Yu ,  Din-I Tsai ,  Jeffrey Dwork ,  Jerry Kuo

Inventor： Ching Yu ,  Din-I Tsai ,  Jeffrey Dwork ,  Jerry Kuo

IPC: H02H305

CPC classification number: G06F11/2236

Abstract: A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.

Abstract translation: 用于在调试模式下冻结通信设备的系统具有时钟控制电路，其被布置为响应于外部时钟信号产生内部时钟信号。 当停止信号被置位时，内部时钟信号被固定在其关闭状态。 结果，内部时钟信号提供的内部寄存器的操作在选定状态下冻结。 可以执行扫描测试以检查所选状态下的内部寄存器。 提供旁路时钟信号来控制内部时钟信号，以便将内部寄存器从一个状态移动到另一个状态。 因此，可能会重新创建导致错误的事件。

公开(公告)号：US06370642B1

公开(公告)日：2002-04-09

申请号：US09316180

申请日：1999-05-21

Applicant: John M. Chiang ,  Ching Yu

Inventor： John M. Chiang ,  Ching Yu

IPC: G06F900

CPC classification number: G06F12/0223 ,  G06F12/0653

Abstract: A system is provided to support programming the size of a board-specific boot ROM in an embedded control system. Depending on functions performed by the embedded control system, a manufacturer decides which storage size of the boot ROM is required. An EEPROM of the embedded system is programmed to represent the selected boot ROM size. A network interface that provides data communications between the embedded control system and a data network has a boot ROM size detection circuit that supports boot ROM size programming. The boot ROM size detection circuit includes a ROM range register programmable from the EEPROM, and a boot ROM base address register programmable by an embedded controller via a PCI bus. During a power up process, the boot ROM size data from the EEPROM are loaded into the ROM range register. The embedded controller writes a predetermined value into the boot ROM base address register so as to read information representing the selected boot ROM size. Based on this information, the embedded controller assigns memory addresses in the network interface for the boot ROM of the selected size.

Abstract translation: 提供了一种系统，用于支持在嵌入式控制系统中对板特定引导ROM的大小进行编程。 根据嵌入式控制系统执行的功能，制造商决定需要启动ROM的存储大小。 嵌入式系统的EEPROM被编程为表示所选择的引导ROM大小。 在嵌入式控制系统和数据网络之间提供数据通信的网络接口具有支持引导ROM大小编程的引导ROM大小检测电路。 引导ROM大小检测电路包括可从EEPROM编程的ROM范围寄存器，以及通过PCI总线由嵌入式控制器可编程的引导ROM基地址寄存器。 在加电过程中，来自EEPROM的引导ROM大小数据被加载到ROM范围寄存器中。 嵌入式控制器将预定值写入引导ROM基地址寄存器，以便读取表示所选引导ROM大小的信息。 基于该信息，嵌入式控制器为所选大小的引导ROM分配网络接口中的存储器地址。

公开(公告)号：US6115779A

公开(公告)日：2000-09-05

申请号：US234456

申请日：1999-01-21

Applicant: Pierre P. Haubursin ,  Ching Yu

Inventor： Pierre P. Haubursin ,  Ching Yu

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2406

Abstract: An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.

Abstract translation: 一种中断管理系统，使用户能够以实时操作模式或批处理操作模式处理中断事件。 在实时模式中，响应于每个中断事件，中断请求信号被断言。 在批处理模式中，中断请求信号被延迟直到检测到预定数量的中断事件，或直到从上一个中断事件被捕获起经过了预定的时间间隔为止。 响应于中断事件，中断寄存器中的相应位被设置为活动状态。 在每个中断的中断控制寄存器中都提供一个控制中断位，以响应中断事件使能中断请求引脚的激活。 在每个中断事件的批处理寄存器中提供了一批批使能位，以使中断事件能够进行批处理。

公开(公告)号：US07984180B2

公开(公告)日：2011-07-19

申请号：US11255124

申请日：2005-10-20

Applicant: Steve L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

Inventor： Steve L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

IPC: H04L12/56

CPC classification number: G06F17/30867 ,  G06F17/30864 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/621 ,  H04L49/90 ,  H04L67/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162 ,  H04L69/163 ,  H04L69/164 ,  H04L69/22 ,  Y10S707/922

Abstract: Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

Abstract translation: 大致描述了网络接口设备被分配最大的搜索范围。 散列函数被应用于每个输入分组的报头信息，以产生分组的哈希码。 哈希代码指定在其中应当找到特定头部信息的表的特定子集，并且在该子集内进行迭代搜索。 如果搜索在超出搜索限制之前找到匹配的条目，则传入数据包将被传递到匹配条目中标识的接收队列。 但是，如果在找到匹配的条目之前搜索达到搜索限制，则设备会将数据包传递到主机系统中的默认队列（如内核队列）。 然后，内核负责将数据包传递到正确的端点。

公开(公告)号：US20080253497A1

公开(公告)日：2008-10-16

申请号：US11733248

申请日：2007-04-10

Applicant: Norman R. Singleton ,  David A. Altman ,  Ching Yu ,  James A. Rex ,  David R. Forsyth

Inventor： Norman R. Singleton ,  David A. Altman ,  Ching Yu ,  James A. Rex ,  David R. Forsyth

IPC: G21C7/08

CPC classification number: G21C13/02 ,  G21Y2002/201 ,  G21Y2002/301 ,  G21Y2002/402 ,  G21Y2004/30 ,  Y02E30/40

Abstract: In a pressurized water reactor with ail of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.

Abstract translation: 在具有核心仪器的一部分的加压水反应器中，通过反应器头进入核心，将引入仪器的每个燃料组件与上部内部仪器仪表导轨对准。 在上部内部上部支撑组件上方的高度中，仪器由作为仪表导向器一部分的上部安装的仪表柱保护和对准，并且从上部支撑组件朝向反应器头部以色调以相应的头部穿透延伸。 上部安装的仪器支架在一端通过上导向管横向支撑，另一端由上支撑板支撑。

公开(公告)号：US20070115982A1

公开(公告)日：2007-05-24

申请号：US11255124

申请日：2005-10-20

Applicant: Steve Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Chiang ,  Der-Ren Chu

Inventor： Steve Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Chiang ,  Der-Ren Chu

IPC: H04L12/56

CPC classification number: G06F17/30867 ,  G06F17/30864 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/621 ,  H04L49/90 ,  H04L67/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162 ,  H04L69/163 ,  H04L69/164 ,  H04L69/22 ,  Y10S707/922

Abstract: Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

Abstract translation: 大致描述了网络接口设备被分配最大的搜索范围。 散列函数被应用于每个输入分组的报头信息，以产生分组的哈希码。 哈希代码指定在其中应当找到特定头部信息的表的特定子集，并且在该子集内进行迭代搜索。 如果搜索在超出搜索限制之前找到匹配的条目，则传入数据包将被传递到匹配条目中标识的接收队列。 但是，如果在找到匹配的条目之前搜索达到搜索限制，则设备会将数据包传递到主机系统中的默认队列（如内核队列）。 然后，内核负责将数据包传递到正确的端点。