公开(公告)号：US20080268631A1

公开(公告)日：2008-10-30

申请号：US11741064

申请日：2007-04-27

申请人： Frank Scott Johnson ,  Freidoon Mehrad

发明人： Frank Scott Johnson ,  Freidoon Mehrad

IPC分类号： H01L21/8238 ,  H01L21/311

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/66545

摘要： A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.

摘要翻译： 一种用于制造半导体器件的方法包括利用CMP叠层形成硅化栅。 CMP堆叠包括形成在下面的半导体器件上的第一衬垫和形成在第一衬里层上的第一介电层。 第一电介质层形成为大约高度的栅极。 在第一介电层上形成第二衬里层。 由于第一电介质层形成为大致高度的栅极，护套区域上的第二衬垫大约在栅极上的第一衬垫的高度处。 执行CMP处理以在栅极的顶部上露出第一衬垫。 由于第一电介质层形成到栅极的高度，所以在CMP工艺之后，第二衬里的一部分保留在护环区域之上。 之后，露出栅极，进行硅化处理以形成硅化栅极。

公开(公告)号：US20080265345A1

公开(公告)日：2008-10-30

申请号：US12135910

申请日：2008-06-09

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L49/00

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

公开(公告)号：US20070037342A1

公开(公告)日：2007-02-15

申请号：US11201924

申请日：2005-08-11

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525上方，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525上。在栅极结构230的顶表面暴露的情况下，金属被结合到栅极结构中以形成栅电极230。

公开(公告)号：US20050059228A1

公开(公告)日：2005-03-17

申请号：US10662850

申请日：2003-09-15

申请人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

发明人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

公开(公告)号：US06765257B1

公开(公告)日：2004-07-20

申请号：US09120712

申请日：1998-07-22

申请人： Freidoon Mehrad ,  Kyle A. Picone

发明人： Freidoon Mehrad ,  Kyle A. Picone

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

摘要翻译： 在FLASH EPROM单元中，水平和垂直源极线之间的源极扩散连续性由垂直源极线下的堆叠下的砷注入提供。

公开(公告)号：US06451642B1

公开(公告)日：2002-09-17

申请号：US09599377

申请日：2000-06-22

申请人： Freidoon Mehrad ,  Jie Xia ,  Thomas M. Ambrose

发明人： Freidoon Mehrad ,  Jie Xia ,  Thomas M. Ambrose

IPC分类号： H01L218238

CPC分类号： H01L27/11526 ,  H01L21/31138 ,  H01L21/32137 ,  H01L27/105 ,  H01L27/11546

摘要： A method to implant NMOS polycrystalline silicon in embedded FLASH memory applications is described. In the method the polycrystalline silicon region (130) that will used to form the gate electrode of the NMOS transistor is doped simultaneously along with the source line in the FLASH memory array.

摘要翻译： 描述了在嵌入式FLASH存储器应用中注入NMOS多晶硅的方法。 在该方法中，将用于形成NMOS晶体管的栅极的多晶硅区域（130）与闪存存储器阵列中的源极线同时掺杂。

公开(公告)号：US06429093B1

公开(公告)日：2002-08-06

申请号：US09627258

申请日：2000-07-28

申请人： Jie Xia ,  Freidoon Mehrad ,  Mercer L. Brugler

发明人： Jie Xia ,  Freidoon Mehrad ,  Mercer L. Brugler

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/823481 ,  H01L27/115 ,  H01L29/66545

摘要： A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (127) to protect the stack during the silicidation process.

摘要翻译： 一种形成具有导电线（24）和穿过沟槽（72）的硅化物区域（140）的半导体部件的方法。 该方法包括在硅化过程中形成氮化物侧壁（127）以保护堆叠。

公开(公告)号：US06268248B1

公开(公告)日：2001-07-31

申请号：US09215478

申请日：1998-12-18

申请人： Freidoon Mehrad

发明人： Freidoon Mehrad

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72) may include forming the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

摘要翻译： 形成具有穿过沟槽（72）的导线（24）的半导体部件的方法可以包括在半导体衬底（52）中形成沟槽（72）。 掺杂剂可以以第一能级注入到半导体衬底（52）中以形成第一导电区域（92）。 掺杂剂可以以第二能级注入到半导体衬底（52）中以形成第二导电区域（94）。 第一能级可能大于第二能级。 第一导电区域（92）和第二导电区域（94）可以形成导线（24）。

公开(公告)号：US07670952B2

公开(公告)日：2010-03-02

申请号：US11690643

申请日：2007-03-23

申请人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

发明人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

IPC分类号： H01L21/311

CPC分类号： H01L21/823835 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/823871

摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。 该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。 清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。 该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

公开(公告)号：US20090191675A1

公开(公告)日：2009-07-30

申请号：US12022488

申请日：2008-01-30

申请人： Freidoon Mehrad ,  Frank S. Johnson

发明人： Freidoon Mehrad ,  Frank S. Johnson

IPC分类号： H01L21/8238

CPC分类号： H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A layer of silicidation metal is formed and a first silicide anneal changes the undoped polysilicon gate electrodes into partially silicided gate electrodes. Dopants of a first type and a second type are implanted into the partially silicided gate electrode of the PMOS and NMOS transistors and a second silicide anneal is performed to change the doped partially silicided gate electrodes into fully silicided gate electrodes.

摘要翻译： 一种制造CMOS晶体管的方法，包括形成NMOS晶体管和具有未掺杂多晶硅栅电极和硬掩模的PMOS晶体管。 该方法还包括形成绝缘材料层，然后去除硬掩模和绝缘材料层的一部分。 形成硅化金属层，并且第一硅化物退火将未掺杂的多晶硅栅电极改变成部分硅化栅电极。 将第一类型和第二类型的掺杂剂注入到PMOS和NMOS晶体管的部分硅化物栅电极中，并且执行第二硅化物退火以将掺杂的部分硅化栅电极改变为完全硅化的栅电极。