公开(公告)号：US6162693A

公开(公告)日：2000-12-19

申请号：US389295

申请日：1999-09-02

申请人： Zhongze Wang ,  Rongsheng Yang

发明人： Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66537 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66575

摘要： A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

公开(公告)号：US6093661A

公开(公告)日：2000-07-25

申请号：US386076

申请日：1999-08-30

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21/8234 ,  H01L21/31 ,  H01L21/336

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

公开(公告)号：US09875788B2

公开(公告)日：2018-01-23

申请号：US12731668

申请日：2010-03-25

申请人： Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

发明人： Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

公开(公告)号：US20140070364A1

公开(公告)日：2014-03-13

申请号：US13613008

申请日：2012-09-13

申请人： Yong Park ,  Zhongze Wang ,  John J. Zhu ,  Choh Fei Yeap

发明人： Yong Park ,  Zhongze Wang ,  John J. Zhu ,  Choh Fei Yeap

IPC分类号： H01L23/525

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/101 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.

摘要翻译： 电可编程栅极氧化物反熔丝器件包括具有抗熔丝链路的抗熔丝孔，所述抗熔丝孔包括其间具有介电层的金属和/或半导体电极。 介电层可以是层间电介质（ILD），金属间电介质（IMD）或蚀刻停止层。 反熔丝器件可以包括具有设置在衬底的表面上的导电栅极（例如，高K金属栅极）和设置在导电栅极上的介电层的半导体衬底。 堆叠的触点可以设置在电介质层上，并且栅极触点设置在栅极的暴露部分上。

公开(公告)号：US08623748B2

公开(公告)日：2014-01-07

申请号：US13169336

申请日：2011-06-27

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L21/04

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

摘要： A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

摘要翻译： 提供了一种用于在掺杂剂注入和激活之后使用氮注入和退火来降低栅极氧化物的有效厚度的方法。 更具体地说，本发明提供一种用于制造半导体器件的方法，例如晶体管，其包括硬化的栅极氧化物，其特征可以在多晶硅/栅极氧化物界面处具有相对较大的氮浓度， 栅极氧化物和栅极氧化物/衬底界面处。 另外，本发明提供了一种用于制造半导体器件的方法，该半导体器件具有设置在其多晶硅层上的金属栅极带（例如，金属硅化物层），该器件包括硬化的栅极氧化物，并且其特征可以是相对较大的氮 在硅化物/多晶硅界面处的浓度基本上防止交叉扩散。

公开(公告)号：US08558320B2

公开(公告)日：2013-10-15

申请号：US12638557

申请日：2009-12-15

申请人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

发明人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

IPC分类号： H01L27/092

CPC分类号： H01L27/0207 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

摘要翻译： 一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。 集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。 导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。 导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

公开(公告)号：US20110235406A1

公开(公告)日：2011-09-29

申请号：US12731668

申请日：2010-03-25

申请人： Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

发明人： Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C11/412

摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

摘要翻译： 5晶体管静态随机存取存储器（5T SRAM）设计用于减小电池尺寸和对工艺变化的抗扰性。 5T SRAM包括用于存储数据的存储元件，其中存储元件耦合到第一电压和接地电压。 存储元件可以包括对称尺寸的交叉耦合的反相器。 单个存取晶体管控制对存储元件的读取和写入操作。 控制逻辑被配置为产生与读取操作的第一电压的值不同的写入操作的第一电压的值。

公开(公告)号：US20060270208A1

公开(公告)日：2006-11-30

申请号：US11499134

申请日：2006-08-03

申请人： Zhongze Wang ,  Michael Violette ,  Jigish Trivedi

发明人： Zhongze Wang ,  Michael Violette ,  Jigish Trivedi

IPC分类号： H01L21/44 ,  H01L21/82

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

摘要翻译： 用于集成电路和半导体器件的保险丝及其使用方法。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层的难熔金属氮化物层。 可以在制造包括相同材料的局部互连结构的过程中制造半导体熔丝。 可以用于编程冗余电路的保险丝可以由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束熔断的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

公开(公告)号：US06949479B2

公开(公告)日：2005-09-27

申请号：US09881407

申请日：2001-06-13

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： The invention includes a method of forming a transistor device. A semiconductor substrate is provided. The substrate has a silicon-comprising surface. The silicon-comprising surface is exposed to activated nitrogen for a time of at least about 20 seconds to convert the silicon-comprising surface to a material comprising silicon and nitrogen. The activated nitrogen is formed by exposing a nitrogen-containing precursor to a plasma generated at a power of at least about 750 watts. A transistor gate structure is formed over the material comprising silicon and nitrogen. The transistor gate structure defines a channel region underlying it. The material comprising silicon and nitrogen separates the transistor gate structure from the channel region. A pair of source/drain regions are formed which are separated from one another by the channel region.

摘要翻译： 本发明包括一种形成晶体管器件的方法。 提供半导体衬底。 衬底具有含硅表面。 将含硅表面暴露于活性氮至少约20秒的时间以将含硅表面转化为包含硅和氮的材料。 活性氮通过将含氮前体暴露于以至少约750瓦的功率产生的等离子体而形成。 在包含硅和氮的材料上形成晶体管栅极结构。 晶体管栅结构限定了其下的沟道区。 包括硅和氮的材料将晶体管栅极结构与沟道区分离。 形成一对源极/漏极区，其通过沟道区彼此分离。

公开(公告)号：US06930029B2

公开(公告)日：2005-08-16

申请号：US10263921

申请日：2002-10-03

申请人： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

发明人： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC分类号： H01L21/285 ,  H01L21/314 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

摘要： A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

摘要翻译： 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 一般来说，钝化层包含Si x O x N z N z。